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M16C/62P Group (M16C/62P, M16C/62PT)
PLL Control Register 0
b7
b6
b5
b4
b3
0
0 1
NOTES:
1. Write to this register after setting the PRC0 bit in the PRCR register to "1" (write enable).
2. When the PM21 bit in the PM2 register is "1" (clock modification disable), writing to this register has no effect.
3. These three bits can only be modified when the PLC07 bit = 0 (PLL turned off). The value once written to this bit
cannot be modified.
4. Before setting this bit to "1," set the CM07 bit in the CM0 register to "0" (main clock), set the CM17 to CM16
bits in the CM1 register to "00b" (main clock undivided mode), and set the CM06 bit in the CM0 register to
"0" (CM16 and CM17 bits enable).
Figure 10.6 PLC0 Register
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
(1, 2)
b2
b1
b0
Symbol
PLC0
Bit
Symbol
PLL Multiplying Factor
PLC00
Select Bit
PLC01
PLC02
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
(b3)
Reserved Bit
(b4)
Reserved Bit
(b6-b5)
Operation Enable Bit
PLC07
page 71
f o
3
6
4
Address
001Ch
Bit Name
b2
b1b0
0 0 0:
Do not set
(3)
0 0 1: Multiply by 2
0 1 0: Multiply by 4
0 1 1: Multiply by 6
1 0 0: Multiply by 8
1 0 1:
1 1 0:
Do not set
1 1 1:
Set to "1"
Set to "0"
0: PLL Off
(4)
1: PLL On
10. Clock Generating Circuit
After Reset
0001X010b
Function
RW
RW
RW
RW
RW
RW
RW
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