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M16C/62P Group (M16C/62P, M16C/62PT)
10.1.3 On-chip Oscillator Clock
This clock, approximately 1MHz, is supplied by a on-chip oscillator. This clock is used as the clock
source for the CPU and peripheral function clocks. In addition, if the PM22 bit in the PM2 register is "1"
(on-chip oscillator clock for the watchdog timer count source), this clock is used as the count source for
the watchdog timer (Refer to 13.1 Count Source Protective Mode).
After reset, the on-chip oscillator is turned off. It is turned on by setting the CM21 bit in the CM2 register
to "1" (on-chip oscillator clock), and is used as the clock source for the CPU and peripheral function
clocks, in place of the main clock. If the main clock stops oscillating when the CM20 bit in the CM2
register is "1" (oscillation stop, re-oscillation detection function enabled) and the CM27 bit is "1" (oscilla-
tion stop, re-oscillation detection interrupt), the on-chip oscillator automatically starts operating, supplying
the necessary clock for the microcomputer.
10.1.4 PLL Clock
The PLL clock is generated PLL frequency synthesizer. This clock is used as the clock source for the
CPU and peripheral function clocks. After reset, the PLL clock is turned off. The PLL frequency synthe-
sizer is activated by setting the PLC07 bit to "1" (PLL operation). When the PLL clock is used as the clock
source for the CPU clock, wait tsu(PLL) for the PLL clock to be stable, and then set the CM11 bit in the
CM1 register to "1".
Before entering wait mode or stop mode, be sure to set the CM11 bit to "0" (CPU clock source is the main
clock). Furthermore, before entering stop mode, be sure to set the PLC07 bit in the PLC0 register to "0"
(PLL stops). Figure 10.9 shows the procedure for using the PLL clock as the clock source for the CPU.
The PLL clock frequency is determined by the equation below.
PLL clock frequency=f(XIN) X (multiplying factor set by the PLC02 to PLC00 bits in the PLC0 register
The PLC02 to PLC00 bits can be set only once after reset. Table 10.2 shows the example for setting PLL
clock frequencies.
Table 10.2 Example for Setting PLL Clock Frequencies
XIN
PLC02
(MHz)
10
0
5
0
3.33
0
2.5
1
12
0
6
0
4
0
3
1
NOTES :
1. 10MHz ≤ PLL clock frequency ≤ 24MHz.
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
(However, 10 MHz ≤ PLL clock frequency ≤ 24 MHz)
PLC01
PLC00
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
page 74
f o
3
6
4
10. Clock Generating Circuit
Multiplying Factor
2
4
6
8
2
4
6
8
PLL Clock
(1)
(MHz)
20
24
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