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M16C/62P Group (M16C/62P, M16C/62PT)
Table 8.8 Bit and Bus Cycle Related to Software Wait
Area
Bus Mode
SFR
Internal
RAM, ROM
Separate Bus
External
Area
Multiplexed
(2)
Bus
NOTES :
1. To use the RDY signal, set this bit to "0".
2. To access in multiplexed bus mode, set the corresponding bit of CS0W to CS3W to "0" (with wait state).
3. When the selected CPU clock source is the PLL clock, the number of wait cycles can be altered by the PM20 bit in the PM2 register. When using a
16 MHz or higher PLL clock, be sure to set the PM20 bit to "0" (2 wait cycles).
4. After reset, the PM17 bit is set to "0" (without wait state), all of the CS0W to CS3W bits are set to "0" (with wait state), and the CSE register is set to
"00h" (one wait state for CS0 to CS3). Therefore, the internal RAM and internal ROM are accessed with no wait states, and all external areas are
accessed with one wait state.
5. When PM17 bit is set to "1" and accesses an external area, set the CSiW (i=0 to 3) bits to "0" (with wait state).
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
PM2 Register
PM1 Register
(5)
PM17 Bit
PM20 Bit
0
1
0
1
0
1
1
page 54
f o
3
6
4
CSR Register
CSE Register
(1)
CS3W Bit
CSE31W to CSE30W Bit
(1)
CSE21W to CSE20W Bit
CS2W Bit
(1)
CSE11W to CSE10W Bit
CS1W Bit
CSE01W to CSE00W Bit
(1)
CS0W Bit
1
00b
0
00b
0
01b
0
10b
0
00b
0
00b
0
01b
0
10b
0
00b
Software Wait
Bus Cycle
(3)
2 BCLK cycle
(3)
3 BCLK cycle
No wait
(4)
1 BCLK cycle
1 wait
2 BCLK cycles
1 BCLK cycle (read)
No wait
2 BCLK cycles (write)
(4)
1 wait
2 BCLK cycles
2 waits
3 BCLK cycles
3 waits
4 BCLK cycles
1 wait
2 BCLK cycles
1 wait
3 BCLK cycles
2 waits
3 BCLK cycles
3 waits
4 BCLK cycles
1 wait
3 BCLK cycles
8. Bus
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