M16C/62P Group (M16C/62P, M16C/62PT)
A/D Control Register 0
b7
b6
b5
b4
b3
b2
1 0
NOTES :
1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.
A/D Control Register 1
b7
b6
b5
b4
b3
b2
1
0
NOTES:
1. If the ADCON1 register is rewritten during A/D conversion, the conversion result will be indeterminate.
2. AN0_0 to AN0_7, and AN2_0 to AN2_7 can be used in the same way as AN0 to AN7. Use the ADGSEL1 to
ADGSEL0 bits in the ADCON2 register to select the desired pin. However, if VCC2 < VCC1, do not use AN0_0
to AN0_7 and AN2_0 to AN2_7 as analog input pins.
3. If the VCUT bit is reset from "0" (Vref unconnected) to "1" (Vref connected), wait for 1 µs or more before starting
A/D conversion.
Figure 18.6 ADCON0 Register and ADCON1 Register (Single Sweep Mode)
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
(1)
b1
b0
Symbol
ADCON0
Bit Symbol
Bit Name
Analog Input Pin
CH0
Select Bit
CH1
CH2
MD0
A/D Operation Mode
Select Bit 0
MD1
TRG
Trigger Select Bit
A/D Conversion
ADST
Start Flag
CKS0
Frequency Select Bit 0
(1)
b1
b0
Symbol
ADCON1
Bit Symbol
Bit Name
A/D Sweep Pin
SCAN0
Select Bit
SCAN1
A/D Operation Mode
MD2
Select Bit 1
8/10-Bit Mode Select Bit
BITS
CKS1
Frequency Select Bit 1
VCUT
Vref Connect Bit
External Op-Amp
OPA0
Connection Mode Bit
OPA1
page 216
f o
3
6
4
Address
After Reset
03D6h
00000XXXb
Invalid in single sweep mode
b4 b3
1 0 : Single sweep mode
0 : Software trigger
1 : ADTRG trigger
0 : A/D conversion disabled
1 : A/D conversion started
Refer to NOTE 3 for the ADCON2 Register
Address
After Reset
03D7h
00h
When single sweep mode is selected
b1 b0
0 0 : AN0 to AN1 (2 pins)
0 1 : AN0 to AN3 (4 pins)
1 0 : AN0 to AN5 (6 pins)
1 1 : AN0 to AN7 (8 pins)
Set to "0" when single sweep mode is selected
0 : 8-bit mode
1 : 10-bit mode
Refer to NOTE 3 for the ADCON2 Register
(3)
1 : Vref connected
b7 b6
0 0 : ANEX0 and ANEX1 are not used
0 1 : Do not set to this value
1 0 : Do not set to this value
1 1 : External op-amp connection mode
18. A/D Converter
Function
Function
(2)
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW