Table of Contents
Advertisement
M16C/62P Group (M16C/62P, M16C/62PT)
17.1.3.1 Detection of Start and Stop Condition
Whether a start or a stop condition has been detected is determined.
A start condition-detected interrupt request is generated when the SDAi pin changes state from high to
low while the SCLi pin is in the high state. A stop condition-detected interrupt request is generated
when the SDAi pin changes state from low to high while the SCLi pin is in the high state.
Because the start and stop condition-detected interrupts share the interrupt control register and vec-
tor, check the BBS bit in the UiSMR register to determine which interrupt source is requesting the
interrupt.
3 to 6 cycles < duration for setting-up
3 to 6 cycles < duration for holding
(Start condition)
(Stop condition)
i = 0 to 2
NOTES :
1. When the PCLK1 bit in the PCLKR register = 1, this is the cycle number of
Figure 17.23 Detection of Start and Stop Condition
17.1.3.2 Output of Start and Stop Condition
A start condition is generated by setting the STAREQ bit in the UiSMR4 register (i = 0 to 2) to "1"
(start).
A restart condition is generated by setting the RSTAREQ bit in the UiSMR4 register to "1" (start).
A stop condition is generated by setting the STPREQ bit in the UiSMR4 register to "1" (start).
The output procedure is described below.
(1) Set the STAREQ bit, RSTAREQ bit or STPREQ bit to "1" (start).
(2) Set the STSPSEL bit in the UiSMR4 register to "1" (output).
The function of the STSPSEL bit is shown in Table 17.14 and Figure 17.24.
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
SCLi
SDAi
SDA i
f1SIO, and the PCLK1 bit = 0, this is the cycle number of f2SIO.
page 186
f o
3
6
4
(1)
(1)
Duration for
Duration for
setting up
holding
17. Serial I/O
Advertisement
Table of Contents
