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M16C/62P Group (M16C/62P, M16C/62PT)
S I/Oi Control Register (i = 3, 4)
b7 b6 b5 b4 b3 b2 b1 b0
NOTES :
1. Make sure this register is written to by the next instruction after setting the PRC2 bit in the PRCR register to "1"
(write enable).
2. Set the SMi3 bit to "1" and the corresponding port direction bit to "0" (input mode).
3. Set the SMi3 bit to "1" (SOUTi output, CLKi function).
4. When the SMi2 bit is set to "1," the target pin goes to a high-impedance state regardless of which function of the
pin is being used.
SI/Oi Bit Rate Generator (i = 3, 4)
b7
NOTES :
1. Write to this register while serial I/O is neither transmitting nor receiving.
2. Use MOV instruction to write to this register.
SI/Oi Transmit/Receive Register (i = 3, 4)
b7
NOTES :
1. Write to this register while serial I/O is neither transmitting nor receiving.
2. To receive data, set the corresponding port direction bit for SINi to "0" (input mode).
Figure 17.35 S3C and S4C Registers, S3BRG and S4BRG Registers, and S3TRR and S4TRR Registers
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
(1)
Symbol
S3C
S4C
Bit
Bit Name
Symbol
SMi0
Internal Synchronous
Clock Select Bit
SMi1
SMi2
SOUTi Output Disable
(4)
Bit
S I/Oi Port Select Bit
SMi3
CLK Polarity Select Bit
SMi4
SMi5
Transfer Direction
Select Bit
SMi6
Synchronous Clock
Select Bit
SMi7
SOUTi Initial Value
Set Bit
(1, 2)
Symbol
b0
S3BRG
S4BRG
Description
Assuming that set value = n, BRGi divides the count
source by n + 1
b0
Symbol
S3TRR
S4TRR
Transmission/reception starts by writing transmit data to this register. After
transmission/reception finishes, reception data can be read by reading this register.
page 203
f o
3
6
4
Address
After Reset
0362h
01000000b
0366h
01000000b
b1 b0
0 0 : Selecting f1SIO or f2SIO
0 1 : Selecting f8SIO
1 0 : Selecting f32SIO
1 1 : Do not set to this value
0 : SOUTi output
1 : SOUTi output disable (High-Impedance)
0 : Input/output port
1 : SOUTi output, CLKi function
0 : Transmit data is output at falling edge of
transfer clock and receive data is input at
rising edge
1 : Transmit data is output at rising edge of
transfer clock and receive data is input at
falling edge
0 : LSB first
1 : MSB first
0 : External clock
1 : Internal clock
Effective when SMi3 = 0
0 : "L" output
1 : "H" output
Address
After Reset
0363h
Indeterminate
0367h
Indeterminate
(1, 2)
Address
0360h
Indeterminate
0364h
Indeterminate
Description
Description
(2)
(3)
Setting Range
00h to FFh
After Reset
17. Serial I/O
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
WO
RW
RW
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