I Flag; Ir Bit; Ilvl2 To Ilvl0 Bits And Ipl - Renesas M16C/62P Hardware Manual

M16C/62P Group (M16C/62P, M16C/62PT)

12.5.1 I Flag

The I flag enables or disables the maskable interrupt. Setting the I flag to "1" (= enabled) enables the
maskable interrupt. Setting the I flag to "0" (= disabled) disables all maskable interrupts.

12.5.2 IR Bit

The IR bit is set to "1" (= interrupt requested) when an interrupt request is generated. Then, when the
interrupt request is accepted and the CPU branches to the corresponding interrupt vector, the IR bit is
cleared to "0" (= interrupt not requested).
The IR bit can be cleared to "0" in a program. Note that do not write "1" to this bit.

12.5.3 ILVL2 to ILVL0 Bits and IPL

Interrupt priority levels can be set using the ILVL2 to ILVL0 bits.
Table 12.3 shows the settings of interrupt priority levels and Table 12.4 shows the interrupt priority levels
enabled by the IPL.
The following are conditions under which an interrupt is accepted:
· I flag = 1
· IR bit = 1
· interrupt priority level > IPL
The I flag, IR bit, ILVL2 to ILVL0 bits and IPL are independent of each other. In no case do they affect one
another.
Table 12.3 Settings of Interrupt Priority Levels
ILVL2 to ILVL0 Bits
000b Level 0 (interrupt disabled)
001b Level 1
010b Level 2
011b Level 3
100b Level 4
101b Level 5
110b Level 6
111b Level 7
R e . v 2 3 . 0 S e p 0 , 1 2 0 0 4
R E J 0 9 B 0 1 8 5 0 - 2 3 0 Z
Interrupt Priority Priority
Level Order
Low
High
f o 3 6 4
page 96
Table 12.4 Interrupt Priority Levels Enabled
by IPL
IPL Enabled Interrupt Priority Levels
000b
Interrupt levels 1 and above are enabled
001b
Interrupt levels 2 and above are enabled
010b
Interrupt levels 3 and above are enabled
011b
Interrupt levels 4 and above are enabled
100b
Interrupt levels 5 and above are enabled
101b
Interrupt levels 6 and above are enabled
110b
Interrupt levels 7 and above are enabled
111b
All maskable interrupts are disabled
12. Interrupt