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M16C/62P Group (M16C/62P, M16C/62PT)
A/D Control Register 2
b7
b6
b5
b4
b3
b2
0
NOTES :
1. If the ADCON2 register is rewritten during A/D conversion, the conversion result will be indeterminate.
2. If VCC2 < VCC1, do not use AN0_0 to AN0_7 and AN2_0 to AN2_7 as analog input pins.
3. The ØAD frequency must be 12 MHz or less. The selected ØAD frequency is determined by a combination of the
CKS0 bit in the ADCON0 register, the CKS1 bit in the ADCON1 register, and the CKS2 bit in the ADCON2 register.
CKS2
0
0
0
0
1
1
1
1
A/D Register i (i=0 to 7)
(b15)
b7
Figure 18.3 ADCON2 Register, and AD0 to AD7 Registers
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
(1)
b1
b0
Symbol
ADCON2
Bit Symbol
A/D Conversion Method
SMP
Select Bit
A/D Input Group Select Bit 0 0 : Port P10 group is selected
ADGSEL0
ADGSEL1
Reserved Bit
(b3)
Frequency Select Bit 2
CKS2
Nothing is assigned.
(b7-b5)
When write, set to "0". When read, their contents are "0".
CKS1
CKS0
0
0
Divide-by-4 of fAD
0
1
Divide-by-2 of fAD
1
0
fAD
1
1
0
0
Ddivide-by-12 of fAD
0
1
Divide-by-6 of fAD
1
0
Divide-by-3 of fAD
1
1
Symbol
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
(b8)
b0
b7
When the BITS bit in the
ADCON1 register is "1"
(10-bit mode)
Eight low-order bits of
A/D conversion result
Two high-order bits of
A/D conversion result
Nothing is assigned.
When write, set to "0". When read, their contents are "0".
page 210
f o
3
6
4
Address
After Reset
03D4h
00h
Bit
Name
0 : Without sample and hold
1 : With sample and hold
b2 b1
0 1 : Do not set
1 0 : Port P0 group is selected
1 1 : Port P2 group is selected
Set to "0"
0: Selects fAD, fAD divided by 2, or
(3)
fAD divided by 4.
1: Selects fAD divided by 3, fAD
divided by 6, or fAD divided by 12.
ØAD
Address
After Reset
03C1h to 03C0h
Indeterminate
03C3h to 03C2h
Indeterminate
03C5h to 03C4h
Indeterminate
03C7h to 03C6h
Indeterminate
03C9h to 03C8h
Indeterminate
03CBh to 03CAh
Indeterminate
03CDh to 03CCh
Indeterminate
03CFh to 03CEh
Indeterminate
b0
Function
When the BITS bit is "0"
(8-bit mode)
A/D conversion result
When read, the content is
indeterminate
18. A/D Converter
Function
RW
RW
RW
(3)
RW
RW
RW
RW
RW
RO
RO
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