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M16C/62P Group (M16C/62P, M16C/62PT)
25. Differences Depending on Manufacturing Period
Tables 25.1 and 25.2 list the precautions are applicable or not applicable every chip version of M16C/62P
flash and ROM external versions. Contact separately about the mask ROM version.
Table 25.1 Technical Update Applicable Table of M16C/62P Flash and ROM External Versions (1)
Ensure that RESET must hold valid-low state during power-on.
When using a reset IC, use a CMOS type IC. When using an open-drain
type reset IC, insert a capacitor between the reset input and VSS. Adjust
the R-C time constant between the capacitor and pull-up resistor at least
10 times longer than the VCC rising time.
If UART0 or UART1 are used as a slave in the I
are placed in a high-impedance state. P6_1 or P6_5 cannot be used as
an output port even if the PD6_1 or PD6_5 bits in the PD6 register are
set to "1" (output mode). Therefore, set the PD6_1 or PD6_5 bits to "0"
(Input mode).
Do not enter wait mode when the main clock or on-chip oscillator clock
is selected as the CPU clock of which division is set by the CM06 bit in
the CM0 register, and the CM16 and CM17 bits in the CM1 register.
The CM05 bit in the CM0 register is set to "0" (main clock oscillation)
and the CM02 bit is set to "1" (peripheral function clock stops in wait
mode).
______
Do not generate an NMI interrupt after entering mode.
Do not generate a voltage detection interruot after entering mode.
I/O ports (P0 to P5) will be indeterminate until internal power supply is
stable, such as when the power is turned on, if "H" is applied to the
CNVSS pin and "L" to the RESET pin while internal power supply is
unstable.
I/O ports (P6 to P14) will be indeterminate until internal power supply is
stable, such as when the power is turned on, if "H" is applied to the
CNVSS pin and "L" to the RESET pin while internal power supply is
unstable.
____________
When the RESET pin is "L" in boot mode (apply "H" to the CNVSS pin
and P5_0 (CE), and "L" to the P5_5 (EPM)), internal pull-up is enabled
for P10_0 to P10_3, P11_0 to P11_7, P12_5 to P12_7, P13_0 to P13_7,
P14_0 and P14_1 and so become "H" level.
P0_0 to P0_7 and P1_0 to P1_7 may become indeterminate when P8_4
____________
is "H" and the RESET pin is "L" in boot mode (apply "H" to the CNVSS
pin and P5_0 (CE), and "L" to P5_5 (EPM)).
P0_0 to P0_7 and P1_0 to P1_7 are in a high impedance state when the
___________
RESET pin and P8_4 are "L".
O
: Applies
–
: Does not apply
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
Precaution
____________
____________
page 357
f o
3
6
4
25. Differences Depending on Manufacturing Period
2
C mode, P6_1 or P6_5
TECHNICAL
Chip version
A
B
C
UPDATE
O
–
–
O
–
–
TN-M16C-100-0309
TN-M16C-108-0309
O
–
–
Precaution 1.1
TN-M16C-108-0309
O
–
–
Precaution 1.2
O
–
–
TN-M16C-108-0309
Precaution 1.3
O
–
–
TN-M16C-108-0309
Precaution 1.4
O
O
O
TN-M16C-114-0310
Precaution 1.1
O
–
–
TN-M16C-114-0310
Precaution 1.1
O
–
–
TN-M16C-114-0310
Precaution 1.2
O
–
–
TN-M16C-114-0310
Precaution 1.3
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