Table of Contents
Advertisement
M16C/62P Group (M16C/62P, M16C/62PT)
If VCC2 < VCC1, do not use AN0_0 to AN0_7 and AN2_0 to AN2_7 as analog input pins.
If the CPU reads the ADi register (i = 0 to 7) at the same time the conversion result is stored in the ADi
register after completion of A/D conversion, an incorrect value may be stored in the ADi register. This
problem occurs when a divide-by-n clock derived from the main clock or a sub-clock is selected for CPU
clock.
• When operating in one-shot or single-sweep mode
Check to see that A/D conversion is completed before reading the target ADi register. (Check the IR bit
in the ADIC register to see if A/D conversion is completed.)
• When operating in repeat mode or repeat sweep mode 0 or 1
Use the main clock for CPU clock directly without dividing it.
If A/D conversion is forcibly terminated while in progress by setting the ADST bit in the ADCON0 register to
"0" (A/D conversion halted), the conversion result of the A/D converter is indeterminate. The contents of ADi
registers irrelevant to A/D conversion may also become indeterminate. If while A/D conversion is underway
the ADST bit is cleared to "0" in a program, ignore the values of all ADi registers.
When setting the ADST bit in the ADCON0 register to "0" in single-sweep mode during A/D conversion and
aborting A/D conversion, disable the interrupt before setting the ADST bit to "0".
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
page 349
f o
3
6
4
24. Usage Precaution
Advertisement
Table of Contents
