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M16C/62P Group (M16C/62P, M16C/62PT)
12.5.5 Interrupt Response Time
Figure 12.5 shows the interrupt response time. The interrupt response or interrupt acknowledge time
denotes a time from when an interrupt request is generated till when the first instruction in the interrupt
routine is executed. Specifically, it consists of a time from when an interrupt request is generated till when
the instruction then executing is completed ((a) on Figure 12.5) and a time during which the interrupt
sequence is executed ((b) on Figure 12.5).
Interrupt request generated
(a) A time from when an interrupt request is generated till when the instruction then
executing is completed. The length of this time varies with the instruction being
executed. The DIVX instruction requires the longest time, which is equal to 30 cycles
(without wait state, the divisor being a register).
(b) A time during which the interrupt sequence is executed. For details, see the table
below. Note, however, that the values in this table must be increased 2 cycles for the
DBC interrupt and 1 cycle for the address match and single-step interrupts.
Interrupt vector address
Figure 12.5 Interrupt response time
12.5.6 Variation of IPL when Interrupt Request is Accepted
When a maskable interrupt request is accepted, the interrupt priority level of the accepted interrupt is set
in the IPL.
When a software interrupt or special interrupt request is accepted, one of the interrupt priority levels listed
in Table 12.5 is set in the IPL. Shown in Table 12.5 are the IPL values of software and special interrupts
when they are accepted.
Table 12.5 IPL Level That is Set to IPL When a Software or Special Interrupt Is Accepted
Interrupt Sources
Watchdog Timer, NMI, Oscillation Stop and Re-Oscillation Detection,
Voltage Down Detection
Software, Address Match, DBC, Single-Step
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
Interrupt request acknowledged
Instruction
Interrupt sequence
(a)
Interrupt response time
SP value
Even
Even
Even
Odd
Odd
Even
Odd
Odd
_______
_________
f o
3
6
4
page 98
Instruction in
interrupt routine
(b)
16-Bit bus, without wait
18 cycles
19 cycles
19 cycles
20 cycles
Time
8-Bit bus, without wait
20 cycles
20 cycles
20 cycles
20 cycles
Level that is Set to IPL
7
Not changed
12. Interrupt
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