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M16C/62P Group (M16C/62P, M16C/62PT)
8.2.9 External Bus Status When Internal Area Accessed
Table 8.7 shows the external bus status when the internal area is accessed.
Table 8.7 External Bus Status When Internal Area Accessed
Item
A0 to A19
D0 to D15
When Read
When Write
RD, WR, WRL, WRH
BHE
CS0 to CS3
ALE
8.2.10 Software Wait
Software wait states can be inserted by using the PM17 bit in the PM1 register, the CS0W to CS3W bits
in the CSR register, and the CSE register. The SFR area is unaffected by these control bits. This area is
always accessed in 2 BCLK or 3 BCLK cycles as determined by the PM20 bit in the PM2 register. See
Table 8.8 Bit and Bus Cycle Related to Software Wait for details.
________
To use the RDY signal, set the corresponding CS3W to CS0W bit to "0" (with wait state). Figure 8.6
shows the CSE register. Table 8.8 shows the software wait related bits and bus cycles. Figure 8.7 and
8.8 show the typical bus timings using software wait.
Chip Select Expansion Control Register
b7
b6
b5
NOTES :
1. Set the CSiW bit (i = 0 to 3) in the CSR register to "0" (with wait state) before writing to the CSEi1W to
CSEi0W bits. If the CSiW bit needs to be set to "1" (without wait state), set the CSEi1W to CSEi0W bits to
"00b" before setting it.
Figure 8.6 CSE Register
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
SFR Accessed
Address output
High-impedance
Output data
RD, WR, WRL, WRH output
BHE output
Output "H"
Output "L"
Symbol
b4
b3
b2
b1
b0
CSE
Bit Symbol
CSE00W
CSE01W
CSE10W
CSE11W
CSE20W
CSE21W
CSE30W
CSE31W
page 53
f o
3
6
4
Address
After Reset
001Bh
00h
Bit Name
b1 b0
CS0 Wait Expansion Bit
(1)
0 0: 1 wait
0 1: 2 waits
1 0: 3 waits
1 1: Do not set
(1)
b3 b2
CS1 Wait Expansion Bit
0 0: 1 wait
0 1: 2 waits
1 0: 3 waits
1 1: Do not set
b5 b4
(1)
CS2 Wait Expansion Bit
0 0: 1 wait
0 1: 2 waits
1 0: 3 waits
1 1: Do not set
b7 b6
(1)
CS3 Wait Expansion Bit
0 0: 1 wait
0 1: 2 waits
1 0: 3 waits
1 1: Do not set
Internal ROM, RAM Accessed
Maintain status before accessed
address of external area or SFR
High-impedance
Undefined
Output "H"
Maintain status before accessed
status of external area or SFR
Output "H"
Output "L"
Function
RW
RW
RW
RW
RW
RW
RW
RW
RW
8. Bus
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