Renesas M16C/62P Hardware Manual page 250

M16C/62P Group (M16C/62P, M16C/62PT)
Port Pi Register (i=0 to 7 and 9 to 13)
b7 b6 b5 b4 b3 b2
NOTES:
1. Since P7_0 and P7_1 are N-channel open drain ports, the data is high-impedance.
2. During memory extension and microprocessor modes, the Pi register for the pins functioning as bus control
pins (A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA and BCLK)
cannot be modified.
3. To use ports P11 to P14, set the PU37 bit in the PUR3 register to "1" (enable). If this bit is set to "0" (disable),
the P11 to P14 registers are cleared to "0".
Port P8 Register
b7 b6 b5 b4 b3 b2
Figure 21.8 P0 to P13 Registers
R e . v 2 3 . 0 S e p 0 , 1 2 0 0 4
R E J 0 9 B 0 1 8 5 0 - 2 3 0 Z
Symbol
P0 to P3 03E0h, 03E1h, 03E4h, 03E5h
b1 b0
P4 to P7 03E8h, 03E9h, 03ECh, 03EDh
P9 to P12 03F1h, 03F4h, 03F5h, 03F8h
P13 03F9h
Bit Symbol
Pi_0 Port Pi_0 Bit
Pi_1 Port Pi_1 Bit
Pi_2 Port Pi_2 Bit
Pi_3 Port Pi_3 Bit
Pi_4 Port Pi_4 Bit
Pi_5 Port Pi_5 Bit
Pi_6 Port Pi_6 Bit
Pi_7 Port Pi_7 Bit
b1 b0
Symbol
P8
Bit Symbol
P8_0 Port P8_0 Bit
P8_1 Port P8_1 Bit
P8_2 Port P8_2 Bit
P8_3 Port P8_3 Bit
P8_4 Port P8_4 Bit
P8_5 Port P8_5 Bit
P8_6 Port P8_6 Bit
P8_7 Port P8_7 Bit
page 236
f o 3 6 4
(2, 3)
Address
Bit Name
The pin level on any I/O port which is
set for input mode can be read by
reading the corresponding bit in this
register.
The pin level on any I/O port which is
set for output mode can be controlled
by writing to the corresponding bit in
this register
0 : "L" level
1 : "H" level
(i = 0 to 7 and 9 to 13)
Address
03F0h
Bit Name
The pin level on any I/O port which is
set for input mode can be read by
reading the corresponding bit in this
register.
The pin level on any I/O port which is
set for output mode can be controlled
by writing to the corresponding bit in
this register (except for P8_5)
0 : "L" level
1 : "H" level
21. Programmable I/O Ports
After Reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Function
(1)
After Reset
Indeterminate
Function
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
RW
RW