Renesas M16C/62P Hardware Manual page 97

M16C/62P Group (M16C/62P, M16C/62PT)
Main clock oscillation
PLL operation mode
CPU clock: f(PLL)
CM07=0
CM06=0
CM17=0
CM16=0
CM04=1 CM04=0
PLL operation
mode
CPU clock: f(PLL)
CM07=0
CM06=0
CM17=0
CM16=0
Sub clock oscillation
NOTES:
1. Avoid making a transition when the CM20 bit in the CM2 register is set to "1" (oscillation stop, re-oscillation detection function enabled).
Set the CM20 bit to "0" (oscillation stop, re-oscillation detection function disabled) before transiting.
2. Wait the main clock oscillation stabilizes.
3. Switch clock after oscillation of sub-clock is sufficiently stable.
4. Change CM17 and CM16 bits in the CM1 register before changing CM06 bit in the CM0 register.
5. Transit in accordance with arrow.
6. The PM20 bit in the PM2 register become effective when the PLC07 bit in the PLC0 register is set to "1" (PLL on). Change the PM20 bit when the PLC07 bit is set to "0" (PLL off).
Set the PM20 bit to "0" (2 waits) when PLL clock >16MHz.
7. PLL operation mode can only be changed to high speed mode. If the PM20 bit = 0 (SFR accessed with two wait states), set PLC07 bit to "0" (PLL off) before setting the PM20 bit to "1"
(SFR accessed with one wait state).
8. Set the CM06 bit to "1" (division by 8 mode) before changing back the operation mode from on-chip oscillator mode to high- or middle-speed mode.
9. When the CM21 bit in the CM2 register = 0 (on-chip oscillator turned off) and the CM05 bit in the CM0 register = 1 (main clock turned off), the CM06 bit is fixed to "1" (divide-by-8 mode) and
the CM15 bit in the CM1 register is fixed to "1" (drive capability High).
Figure 10.11 State Transition in Normal Mode
R e . v 2 3 . 0 S e p 0 , 1 2 0 0 4
R E J 0 9 B 0 1 8 5 0 - 2 3 0 Z
Middle-speed mode
High-speed mode
(divide by 2)
PLC07=1
(6) CPU clock: f(XIN) CPU clock: f(XIN)/2
CM11=1
CM07=0 CM07=0
CM06=0 CM06=0
CM17=0 CM17=0
PLC07=0
(7)
CM16=0 CM16=1
CM11=0
CM04=1
Middle-speed mode
High-speed mode
(divide by 2)
PLC07=1
(6)
CM11=1
CPU clock: f(XIN) CPU clock: f(XIN)/2
CM07=0 CM07=0
CM06=0 CM06=0
PLC07=0
CM17=0 CM17=0
(7)
CM11=0
CM16=0 CM16=1
CM07=1
CM05=1
page 83
f o 3 6 4
Middle-speed mode
Middle-speed mode Middle-speed mode
(divide by 4)
(divide by 8) (divide by 16)
CPU clock: f(XIN)/4
CPU clock: f(XIN)/8 CPU clock: f(XIN)/16
CM07=0 CM07=0
CM07=0
CM06=0 CM06=0
CM17=1 CM17=1
CM06=1
CM16=0 CM16=1
CM04=0
Middle-speed mode
Middle-speed mode Middle-speed mode
(divide by 4)
(divide by 8) (divide by 16)
CPU clock: f(XIN)/4 CPU clock: f(XIN)/8 CPU clock: f(XIN)/16
CM07=0 CM07=0
CM07=0
CM06=0 CM06=0
CM17=1 CM17=1
CM06=1
CM16=0 CM16=1
(3) (2, 4)
CM07=0
Low-speed mode
CM21=0
CPU clock: f(XCIN)
CM07=0
CM21=1
(1, 9)
CM05=0
Low power dissipation mode
CPU clock: f(XCIN)
CM07=0
CM06=1
CM15=1
10. Clock Generating Circuit
On-chip oscillator clock
oscillation
On-chip oscillator low power
On-chip oscillator mode
dissipation mode
CPU clock CPU clock
(8)
CM05=0
CM21=0
f(Ring) f(Ring)
f(Ring)/2 f(Ring)/2
f(Ring)/4 f(Ring)/4
f(Ring)/8 f(Ring)/8
f(Ring)/16 f(Ring)/16
(1)
CM21=1
CM05=1
CM04=1 CM04=0 CM04=1
On-chip oscillator
On-chip oscillator low power
mode dissipation mode
(8)
CPU clock CPU clock
CM21=0
CM05=0 M05 0
f(Ring) f(Ring)
f(Ring)/2 f(Ring)/2
f(Ring)/4 f(Ring)/4
f(Ring)/8 f(Ring)/8
f(Ring)/16 f(Ring)/16
(1)
CM05=1
CM21=1
Low-speed mode
CPU clock: f(XCIN)
CM07=0
CM04=0