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M16C/62P Group (M16C/62P, M16C/62PT)
__________
8.2.7 HOLD Signal
This signal is used to transfer control of the bus from the CPU or DMAC to an external circuit. When the
__________
input on HOLD pin is pulled low, the microcomputer is placed in a hold state after the bus access then in
process finishes. The microcomputer remains in the hold state while the HOLD pin is held low, during
__________
which time the HLDA pin outputs a low-level signal.
Table 8.5 shows the microcomputer status in the hold state.
Bus-using priorities are given to HOLD, DMAC, and CPU in order of decreasing precedence. However,
if the CPU is accessing an odd address in word units, the DMAC cannot gain control of the bus during two
separate accesses.
Figure 8.5 Bus-Using Priorities
Table 8.5 Microcomputer Status in Hold State
BCLK
A0 to A19, D0 to D15, CS0 to CS3, RD, WRL,
_________ _______ _______
WRH, WR, BHE
I/O ports
__________
HLDA
Internal Peripheral Circuits
ALE Signal
NOTES:
1. P11 to P14 are included in the 128-pin version.
2. When I/O port function is selected.
3. The watchdog timer dose not stop when the PM22 bit in the PM2 register is set to "1" (the count
source for the watchdog timer is the on-chip oscillator clock).
8.2.8 BCLK Output
If the PM07 bit in the PM0 register is set to "0" (output enable), a clock with the same frequency as that of
the CPU clock is output as BCLK from the BCLK pin. Refer to 10.2 CPU clock and pheripheral clock.
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
__________
__________
HOLD > DMAC > CPU
Item
_______
_______
_____
________
P0, P1, P3, P4
P6 to P14
page 51
f o
3
6
4
Output
High-impedance
(2)
High-impedance
(1)
Maintains status when HOLD signal is received
Output "L"
ON (but watchdog timer stops)
Undefined
__________
Status
__________
8. Bus
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