Table of Contents
Advertisement
M16C/62P Group (M16C/62P, M16C/62PT)
24.9.2 UART
24.9.2.1 Special Mode 1(I
When generating start, stop and restart conditions, set the STSPSEL bit in the UiSMR4 register to "0"
and wait for more than half cycle of the transfer clock before setting each condition generate bit
(STAREQ,RSTAREQ and STPREQ) from "0" to "1".
24.9.2.2 Special Mode 2
If a low-level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC register = 1 (three-
phase output forcible cutoff by input on NMI pin enabled), the RTS2 and CLK2 pins go to a high-
impedance state.
24.9.2.3 Special Mode 4 (SIM Mode)
A transmit interrupt request is generated by setting the U2C1 register U2IRS bit to "1" (transmission
complete) and U2ERE bit to "1" (error signal output) after reset. Therefore, when using SIM mode, be
sure to clear the IR bit to "0" (no interrupt request) after setting these bits.
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
2
C Mode)
_______
page 346
f o
3
6
4
_______
24. Usage Precaution
_________
Advertisement
Table of Contents
