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M16C/62P Group (M16C/62P, M16C/62PT)
22.3.8 Full Status Check
If an error occurs when a program or erase operation is completed, the FMR06 to FMR07 bits in the
FMR0 register are set to "1", indicating a specific error. Therefore, execution results can be confirmed by
checking these bits (full status check).
Table 22.6 lists errors and FMR0 register state. Figure 22.12 shows a flow chart of the full status check
and handling procedure for each error.
Table 22.6 Errors and FMR0 Register State
FMR00 Register
(Status Register)
State
FMR07 bit
FMR06 bit
(SR5 bit)
(SR4 bit)
1
1
1
0
0
1
NOTES:
1. The flash memory enters read array mode by writing command code "xxFFh" in the second bus cycle
of these commands. The command code written in the first bus cycle becomes invalid.
2. When the FMR02 bit is set to "1" (lock bit disabled), no error occurs even under the conditions above.
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
Error
Command
Sequence error • A value other than "xxD0h" or "xxFFh" is written in the second
Erase error
Program error
page 263
f o
3
6
4
Error Occurrence Conditions
• Command is written incorrectly
bus cycle of the lock bit program, block erase or erase all
unlocked block command
• The block erase command is executed on a locked block
• The block erase or erase all unlocked block command is
executed on an unlock block and auto erase operation is not
completed as expected
• The program command is executed on locked blocks
• The program command is executed on unlocked blocks but
program operation is not completed as expected
• The lock bit program command is executed but program
operation is not completed as expected
22. Flash Memory Version
(1)
(2)
(2)
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