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M16C/62P Group (M16C/62P, M16C/62PT)
Table 21.2 Unassigned Pin Handling in Single-chip Mode
Pin Name
Ports P0 to P7,
P8_0 to P8_4, P8_6 to P8_7,
P9 to P14
(4)
XOUT
NMI
AVCC
AVSS, VREF, BYTE
NOTES:
1. When setting the port for output mode and leave it open, be aware that the port remains in input mode until
it is switched to output mode in a program after reset. For this reason, the voltage level on the pin becomes
indeterminate, causing the power supply current to increase while the port remains in input mode.
Furthermore, by considering a possibility that the contents of the direction registers could be changed by
noise or noise-induced runaway, it is recommended that the contents of the direction registers be
periodically reset in software, for the increased reliability of the program.
2. Make sure the unused pins are processed with the shortest possible wiring from the microcomputer pins
(within 2 cm).
3. When the ports P7_0 and P7_1 are set for output mode, make sure a low-level signal is output from the pins.
The ports P7_0 and P7_1 are N-channel open-drain outputs.
4. With external clock input to XIN pin.
5. Process the port without a pin in the 80-pin version and the 100-pin version as follows.
80-pin version
• Set the direction bits in these ports to "1" (output mode), and set the output data to "0" ("L") using the
program.
• Ports P11 to P14 do not exist.
100-pin version
• After reset, PU37 bit is "0" (P11 to P14 do not used).
Do not write "1" to PU37 bit. When read, value of PU37 bit is indeterminate.
• The port direction bit in the P11 to P14 can be set "0" or "1".
Pin Name
Ports P0 to P7, P8_0 to P8_4,
P8_6 to P8_7, P9 to P14
P4_5 / CS1 to P4_7 / CS3
BHE, ALE, HLDA, XOUT
(6)
BCLK
HOLD, RDY
AVCC
AVSS, VREF
NOTES:
1. When setting the port for output mode and leave it open, be aware that the port remains in input mode until
it is switched to output mode in a program after reset. For this reason, the voltage level on the pin becomes
indeterminate, causing the power supply current to increase while the port remains in input mode.
Furthermore, by considering a possibility that the contents of the direction registers could be changed by
noise or noise-induced runaway, it is recommended that the contents of the direction registers be
periodically reset in software, for the increased reliability of the program.
2. Make sure the unused pins are processed with the shortest possible wiring from the microcomputer pins
(within 2 cm).
3. If the CNVSS pin has the VSS level applied to it, these pins are set for input ports until the processor mode
is switched over in a program after reset. For this reason, the voltage levels on these pins become
indeterminate, causing the power supply current to increase while they remain set for input ports.
4. When the ports P7_0 and P7_1 are set for output mode, make sure a low-level signal is output from the pins.
The ports P7_0 and P7_1 are N-channel open-drain outputs.
5. With external clock input to XIN pin.
6. If the PM07 bit in the PM0 register is set to "1" (BCLK not output), connect this pin to VCC2 via a resistor
(pulled high).
7. Process the port without a pin in the 100-pin version as follows.
• After reset, PU37 bit is "0" (P11 to P14 do not used).
Do not write "1" to PU37 bit. When read, value of PU37 bit is indeterminate.
• The port direction bit in the P11 to P14 can be set "0" or "1".
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
After setting for input mode, connect every pin to VSS via a resistor (pull-down);
or after setting for output mode, leave these pins open.
Open
Connect via resistor to VCC1 (pull-up)
Connect to VCC1
Connect to VSS
After setting for input mode, connect every pin to VSS via a resistor (pull-down);
or after setting for output mode, leave these pins open.
Connect to VCC via a resistor (pulled high) by setting the corresponding
direction bit in the PD4 register for CSi (i=1 to 3) to "0" (input mode) and the
CSi bit in the CSR register to "0" (chip select disabled).
Open
(5)
,
Connect via resistor to VCC2 (pull-up)
Connect to VCC1
Connect to VSS
page 240
f o
3
6
4
Connection
(1, 2, 3, 5)
Connection
(1, 2, 3, 4, 7)
21. Programmable I/O Ports
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