Renesas M16C/62P Hardware Manual page 62

M16C/62P Group (M16C/62P, M16C/62PT)
Example 1
To access the external area indicated by CSj in the next cycle after
accessing the external area indicated by CSi
The address bus and the chip select signal both change state between
these two cycles.
Access to the external
area indicated by CSi
BCLK
Read signal
Data bus
Address bus
CSi
CSj
Example 3
To access the external area indicated by CSi in the next cycle after
accessing the external area indicated by the same CSi
The address bus changes state but the chip select signal does not
change state
Access to the external
area indicated by CSi
BCLK
Read signal
Data bus
Address bus
CSi
NOTES :
1. These examples show the address bus and chip select signal when accessing areas in two successive cycles. The chip select bus cycle
may be extended more than two cycles depending on a combination of these examples.
Shown above is the case where separate bus is selected and the area is accessed for read without wait states. i = 0 to 3, j = 0 to 3
(not including i, however)
Figure 8.2 Example of Address Bus and CSi Signal Output in 1-Mbyte mode
R e . v 2 3 . 0 S e p 0 , 1 2 0 0 4
R E J 0 9 B 0 1 8 5 0 - 2 3 0 Z
Access to the external
area indicated by CSj
Data Data
Address Address
Access to the same
external area
Data Data
Address Address
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f o 3 6 4
Example 2
To access the internal ROM or internal RAM in the next cycle after
accessing the external area indicated by CSi
The chip select signal changes state but the address bus does not
change state
Access to the external
area indicated by CSi
BCLK
Read signal
Data bus
Address bus
CSi
Example 4
Not to access any area (nor instruction prefetch generated) in the next cycle after
accessing the external area indicated by CSi
Neither the address bus nor the chip select signal changes state between
these two cycles
Access to the external
area indicated by CSi
BCLK
Read signal
Data bus
Address bus
CSi
______
Access to the internal
ROM or internal RAM
Data
Address
No access
Data
Address
8. Bus