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M16C/62P Group (M16C/62P, M16C/62PT)
ROM Code Protect Control Address
b7
b6
b5
b4
b3
1
1
1
NOTES:
1. If the ROMCP1 bits are set to other than "11b" (ROM code protect enabled), the flash memory is disabled
against reading and rewriting in parallel I/Ot mode.
2. When the ROMCP1 bits are set to other than "11b," set the bit 5 to bit 0 to "111111b".
3. When exiting ROM code protect, erase the block including the ROMCP1 register by CPU rewrite mode or
standard serial I/O mode.
4. If a memory block that including ROMCP1 register is erased, the ROMCP register is set to "FFh".
Figure 22.2 ROMCP Register
Figure 22.3 Address for ID Code Stored
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
b2
b1
b0
Symbol
1
1
1
ROMCP
Bit Symbol
Reserved Bit
(b0)
Reserved Bit
(b1)
Reserved Bit
(b2)
Reserved Bit
(b3)
Reserved Bit
(b4)
Reserved Bit
(b5)
ROMCP1
ROM Code Protect Level 1
Set Bit
Address
0FFFDFh to 0FFFDCh
0FFFE3h to 0FFFE0h
0FFFE7h to 0FFFE4h
0FFFEBh to 0FFFE8h
0FFFEFh to 0FFFECh
0FFFF3h to 0FFFF0h
0FFFF7h to 0FFFF4h
0FFFFBh to 0FFFF8h
0FFFFFh to 0FFFFCh
page 246
f o
3
6
4
Address
Value When Shipped
0FFFFFh
FFh
Bit Name
Set to "1"
Set to "1"
Set to "1"
Set to "1"
Set to "1"
Set to "1"
b7 b6
0 0:
(1, 2, 3, 4)
0 1:
1 0:
1 1: Protect disabled
ID1
Undefined instruction vector
ID2
Overflow vector
BRK instruction vector
ID3
Address match vector
ID4
Single step vector
ID5
Watchdog timer vector
ID6
DBC vector
ID7
NMI vector
Reset vector
ROMCP
4 bytes
22. Flash Memory Version
(4)
Function
Protect enabled
RW
RW
RW
RW
RW
RW
RW
RW
RW
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