Table of Contents
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10.5 System Clock Protection Function ........................................................................ 85
10.6 Oscillation Stop and Re-oscillation Detect Function ........................................... 85
10.6.1 Operation When CM27 bit = 0 (Oscillation Stop Detection Reset) ........................................... 86
10.6.2 Operation When CM27 bit = 0 (Oscillation Stop and Re-oscillation Detect Interrupt) ............ 86
10.6.3 How to Use Oscillation Stop and Re-oscillation Detect Function ............................................ 87
11. Protection ________________________________________________ 88
12. Interrupt _________________________________________________ 89
12.1 Type of Interrupts ..................................................................................................... 89
12.2 Software Interrupts .................................................................................................. 90
12.2.1 Undefined Instruction Interrupt ................................................................................................... 90
12.2.2 Overflow Interrupt ......................................................................................................................... 90
12.2.3 BRK Interrupt ................................................................................................................................ 90
12.2.4 INT Instruction Interrupt ............................................................................................................... 90
12.3 Hardware Interrupts ................................................................................................. 91
12.3.1 Special Interrupts .......................................................................................................................... 91
12.3.2 Peripheral Function Interrupts .................................................................................................... 91
12.4 Interrupts and Interrupt Vector ............................................................................... 92
12.4.1 Fixed Vector Tables ...................................................................................................................... 92
12.4.2 Relocatable Vector Tables ............................................................................................................ 93
12.5 Interrupt Control ...................................................................................................... 94
12.5.1 I Flag ............................................................................................................................................... 96
12.5.2 IR Bit ............................................................................................................................................... 96
12.5.3 ILVL2 to ILVL0 Bits and IPL .......................................................................................................... 96
12.5.4 Interrupt Sequence ....................................................................................................................... 97
12.5.5 Interrupt Response Time .............................................................................................................. 98
12.5.6 Variation of IPL when Interrupt Request is Accepted ................................................................ 98
12.5.7 Saving Registers ........................................................................................................................... 99
12.5.8 Returning from an Interrupt Routine ......................................................................................... 101
12.5.9 Interrupt Priority .......................................................................................................................... 101
12.5.10 Interrupt Priority Resolution Circuit ........................................................................................ 101
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12.6 INT Interrupt ........................................................................................................... 103
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12.7 NMI Interrupt........................................................................................................... 104
12.8 Key Input Interrupt ................................................................................................. 104
12.9 Address Match Interrupt ....................................................................................... 105
13. Watchdog Timer __________________________________________ 107
13.1 Count source protective mode ............................................................................. 108
13.2 Cold start / Warm start ........................................................................................... 109
14. DMAC ___________________________________________________ 110
14.1 Transfer Cycles ...................................................................................................... 115
14.1.1 Effect of Source and Destination Addresses ........................................................................... 115
14.1.2 Effect of BYTE Pin Level ........................................................................................................... 115
A-3
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