Table of Contents
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1. Overview ___________________________________________________ 1
1.1 Applications ................................................................................................................. 1
1.2 Performance Outline.................................................................................................... 2
1.3 Block Diagram .............................................................................................................. 5
1.4 Product List .................................................................................................................. 7
1.5 Pin Configuration ....................................................................................................... 13
1.6 Pin Description........................................................................................................... 17
2. Central Processing Unit (CPU) ________________________________ 22
2.1 Data Registers (R0, R1, R2 and R3).......................................................................... 22
2.2 Address Registers (A0 and A1) ................................................................................ 22
2.3 Frame Base Register (FB) ......................................................................................... 23
2.4 Interrupt Table Register (INTB) ................................................................................. 23
2.5 Program Counter (PC) ............................................................................................... 23
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) .................................. 23
2.7 Static Base Register (SB) .......................................................................................... 23
2.8 Flag Register (FLG).................................................................................................... 23
2.8.1 Carry Flag (C Flag) .......................................................................................................................... 23
2.8.2 Debug Flag (D Flag) ........................................................................................................................ 23
2.8.3 Zero Flag (Z Flag) ............................................................................................................................ 23
2.8.4 Sign Flag (S Flag) ............................................................................................................................ 23
2.8.5 Register Bank Select Flag (B Flag) ............................................................................................... 23
2.8.6 Overflow Flag (O Flag) .................................................................................................................... 23
2.8.7 Interrupt Enable Flag (I Flag) ......................................................................................................... 23
2.8.8 Stack Pointer Select Flag (U Flag)................................................................................................. 23
2.8.9 Processor Interrupt Priority Level (IPL) ........................................................................................ 23
2.8.10 Reserved Area ............................................................................................................................... 23
3. Memory ___________________________________________________ 24
4. Special Function Register (SFR) ______________________________ 25
5. Reset _____________________________________________________ 31
5.1 Hardware Reset 1 ....................................................................................................... 31
5.1.1 Reset on a Stable Supply Voltage .................................................................................................. 31
5.1.2 Power-on Reset ................................................................................................................................ 31
5.2 Voltage Down Detection Reset (Hardware Reset 2) ................................................ 31
5.3 Software Reset ........................................................................................................... 32
5.4 Watchdog Timer Reset .............................................................................................. 32
5.5 Oscillation Stop Detection Reset ............................................................................. 32
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