Table of Contents
Advertisement
M16C/62P Group (M16C/62P, M16C/62PT)
UARTi Transmit/Receive Mode Register (i=0 to 2)
b7
b6
b5
b4
b3
b2
NOTES :
1. Set the corresponding port direction bit for each CLKi pin to "0" (input mode).
2. To receive data, set the corresponding port direction bit for each RXDi pin to "0" (input mode).
3. Set the corresponding port direction bit for SCL and SDA pins to "0" (input mode).
UARTi Transmit/Receive Control Register 0 (i=0 to 2)
b7
b6
b5
b4
b3
b2
NOTES :
1. Set the corresponding port direction bit for each CTSi pin to "0" (input mode).
2. TXD2/SDA2 and SCL2 are N-channel open-drain output. Cannot be set to the CMOS output. No NCH bit in U2C0 register is
assigned. When write, set to "0".
3. The UFORM bit is enabled when the SMD2 to SMD0 bits in the UiMR register are set to "001b" (clock synchronous serial I/O
mode), or "101b" (UART mode, 8-bit transfer data).
Set this bit to "1" when the SMD2 to SMD0 bits are set to "010b" (I
"100b" (UART mode, 7-bit transfer data) or "110b" (UART mode, 9-bit transfer data).
4. CTS1/RTS1 can be used when the CLKMD1 bit in the UCON register = 0 (only CLK1 output) and the RCSP bit in the UCON
register = 0 (CTS0/RTS0 not separated).
Figure 17.6 U0MR to U2MR Register and U0C0 to U2C0 Register
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
b1
b0
Symbol
U0MR to U2MR
Bit
Bit Name
Symbol
Serial I/O Mode Select
SMD0
Bit
(2)
SMD1
SMD2
CKDIR
Internal/External Clock
Select Bit
Stop Bit Length
STPS
Select Bit
Odd/Even Parity
PRY
Select Bit
Parity Enable Bit
PRYE
TXD, RXD I/O Polarity
IOPOL
Reverse Bit
b1
b0
Symbol
U0C0 to U2C0
03A4h, 03ACh, 037Ch
Bit
Bit Name
Symbol
CLK0
BRG Count Source
Select Bit
CLK1
CTS/RTS Function
CRS
(4)
Select Bit
Transmit Register
TXEPT
Empty Flag
CTS/RTS Disable Bit
CRD
Data Output Select
NCH
(2)
Bit
CLK Polarity Select Bit
CKPOL
UFORM Transfer Format Select
Bit
(3)
page 159
f o
3
6
4
Address
After Reset
03A0h, 03A8h, 0378h
00h
b2 b1 b0
0 0 0 : Serial I/O disabled
0 0 1 : Clock synchronous serial I/O mode
2
0 1 0 : I
C mode
1 0 0 : UART mode transfer data 7 bits long
1 0 1 : UART mode transfer data 8 bits long
1 1 0 : UART mode transfer data 9 bits long
Do not set except above
0 : Internal clock
(1)
1 : External clock
0 : 1 stop bit
1 : 2 stop bits
Effective when PRYE = 1
0 : Odd parity
1 : Even parity
0 : Parity disabled
1 : Parity enabled
0 : No reverse
1 : Reverse
Address
After Reset
00001000b
b1 b0
0 0 : f1SIO or f2SIO is selected
0 1 : f8SIO is selected
1 0 : f32SIO is selected
1 1 : Do not set to this value
Effective when CRD = 0
0 : CTS function is selected
1 : RTS function is selected
0 : Data present in transmit register (during transmission)
1 : No data present in transmit register
(transmission completed)
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P6_0, P6_4 and P7_3 can be used as I/O ports)
0 : TXDi/SDAi and SCLi pins are CMOS output
1 : TXDi/SDAi and SCLi pins are N-channel open-drain output
0 : Transmit data is output at falling edge of transfer clock
and receive data is input at rising edge
1 : Transmit data is output at rising edge of transfer clock
and receive data is input at falling edge
0 : LSB first
1 : MSB first
2
C mode), and to "0" when the SMD2 to SMD0 bits are set to
17. Serial I/O
Function
(3)
Function
(1)
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
RW
RW
RW
RW
Advertisement
Table of Contents
