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M16C/62P Group (M16C/62P, M16C/62PT)
Figure 10.10 shows the state transition from normal operation mode to stop mode and wait mode. Figure
10.11 shows the state transition in normal operation mode.
Table 10.7 shows a state transition matrix describing allowed transition and setting. The vertical line
shows current state and horizontal line shows state after transition.
All oscillators stopped
Stop mode
CM07=0
CM06=1
CM05=0
Stop mode
CM11=0
(5)
CM10=1
Stop mode
Stop mode
NOTES :
1. Do not go directly from PLL operation mode to wait or stop mode.
2. PLL operation mode can be entered from high speed mode. Similarly, PLL operation mode can be changed back to high speed mode.
3. Shown above is the case where the PM21 bit in the PM2 register = 0 (system clock protective function unused).
4. The on-chip oscillator clock divided by 8 provides the CPU clock.
5. Write to the CM0 and CM1 registers per 16 bit with CM21=0 (on-chip oscillator stops).
Since the operation starts from the main clock after exiting stop mode, the time until the CPU operates can be reduced.
6. Before entering stop mode, be sure to clear the CM20 bit in the CM2 register to "0" (oscillation stop and oscillation restart detection function disabled).
Figure 10.10 State Transition to Stop Mode and Wait Mode
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
CM10=1
(6)
Interrupt
Interrupt
(6)
CM10=1
When
low power
When
dissipation
low-
mode
speed
mode
(6)
CM10=1
Low-speed, low power
dissipation mode
Interrupt
(6)
CM10=1
On-chip oscillator, On-chip
oscillator dissipation mode
(4)
Interrupt
page 82
f o
3
6
4
Reset
Medium-speed mode
(divided-by-8 mode)
High-speed, medium-
speed mode
(NOTES 1, 2)
PLL operation
mode
Normal mode
10. Clock Generating Circuit
WAIT
CPU operation stopped
instruction
Wait mode
Interrupt
WAIT
instruction
Wait mode
Interrupt
WAIT
instruction
Wait mode
Interrupt
WAIT
instruction
Wait mode
Interrupt
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