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M16C/62P Group (M16C/62P, M16C/62PT)
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8.2.6 The RDY Signal
This signal is provided for accessing external devices which need to be accessed at low speed. If input
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on the RDY pin is asserted low at the last falling edge of BCLK of the bus cycle, one wait state is inserted
in the bus cycle. While in a wait state, the following signals retain the state in which they were when the
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RDY signal was acknowledged.
A0 to A19, D0 to D15, CS0 to CS3, RD, WRL, WRH, WR, BHE, ALE, HLDA
Then, when the input on the RDY pin is detected high at the falling edge of BCLK, the remaining bus cycle
is executed. Figure 8.4 shows example in which the wait state was inserted into the read cycle by the
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RDY signal. To use the RDY signal, set the corresponding bit (CS3W to CS0W bits) in the CSR register
to "0" (with wait state). When not using the RDY signal, process the RDY pin as an unused pin.
In an instance of separate bus
BCLK
RD
CSi
(i=0 to 3)
RDY
In an instance of multiplexed bus
BCLK
RD
CSi
(i=0 to 3)
RDY
Shown above is the case where CSEi1W to CSEi0W (i = 0 to 3) bits in the CSE register are "00b" (one wait state).
Figure 8.4 Example in which Wait State was Inserted into Read Cycle by RDY Signal
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
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______ ________
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Accept timing of RDY signal
: Wait using RDY signal
: Wait using software
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f o
3
6
4
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tsu(RDY - BCLK)
tsu(RDY - BCLK)
Accept timing of RDY signal
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8. Bus
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