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M16C/62P Group (M16C/62P, M16C/62PT)
DMAi Source Pointer (i = 0, 1)
(b19)
(b23)
b3
b7
NOTES:
1. If the DSD bit in the DMiCON register is "0" (fixed), this register can only be written to when the DMAE bit in the
DMiCON register is "0" (DMA disabled).
If the DSD bit is "1" (forward direction), this register can be written to at any time.
If the DSD bit is "1" and the DMAE bit is "1" (DMA enabled), the DMAi forward address pointer can be read from
this register. Otherwise, the value written to it can be read.
DMAi Destination Pointer (i = 0, 1)
(b19)
(b23)
b3
b7
NOTES:
1. If the DAD bit in the DMiCON register is "0" (fixed), this register can only be written to when the DMAE bit in the
DMiCON register is "0"(DMA disabled).
If the DAD bit is "1" (forward direction), this register can be written to at any time.
If the DAD bit is "1" and the DMAE bit is "1" (DMA enabled), the DMAi forward address pointer can be read from
this register. Otherwise, the value written to it can be read.
DMAi Transfer Counter (i = 0, 1)
(b15)
b7
Figure 14.4 SAR0, SAR1, DAR0, DAR1, TCR0, and TCR1 Registers
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
(1)
(b16)(b15)
(b8)
b0
b7
b0
Set the source address of transfer
Nothing is assigned. When write, set "0".
When read, their contents are "0".
(1)
(b16)
(b15)
(b8)
b0
b7
b0
Set the destination address of transfer
Nothing is assigned. When write, set "0".
When read, their contents are "0".
(b8)
b0
b7
b0
Set the transfer count minus 1. The written value
is stored in the DMAi transfer counter reload
register, and when the DMAE bit in the DMiCON
register is set to "1" (DMA enabled) or the DMAi
transfer counter underflows when the DMASL bit
in the DMiCON register is "1" (repeat transfer),
the value of the DMAi transfer counter reload
register is transferred to the DMAi transfer
counter.
When read, the DMAi transfer counter is read.
page 114
f o
3
6
4
Symbol
b7
b0
SAR0
SAR1
Function
b7
b0
Symbol
DAR0
DAR1
Function
Symbol
TCR0
TCR1
Function
Address
After Reset
0022h to 0020h
Indeterminate
0032h to 0030h
Indeterminate
Setting Range
00000h to FFFFFh
Address
After Reset
0026h to 0024h
Indeterminate
0036h to 0034h
Indeterminate
Setting Range
00000h to FFFFFh
Address
After Reset
0029h, 0028h
Indeterminate
0039h, 0038h
Indeterminate
Setting Range
0000h to FFFFh
14. DMAC
RW
RW
RW
RW
RW
RW
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