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M16C/62P Group (M16C/62P, M16C/62PT)
RXDi
RXD data
reverse circuit
STPS
1SP
0
SP
SP
1
2SP
0
STPS
2SP
1
SP
SP
0
1SP
i=0 to 2
SP: Stop bit
PAR: Parity bit
SMD2 to SMD0, STPS, PRYE, IOPOL, CKDIR: Bits in UiMR register
UiERE: Bit in UiC1 register
Figure 17.4 UARTi Transmit/Receive Unit
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
IOPOL
No reverse
0
1
Reverse
PRYE
Clock
synchronous
PAR
type
disabled
0
0
PAR
1
1
PAR
UART
enabled
SMD2 to SMD0
0
0
0
0
0
PRYE
SMD2 to SMD0
PAR
enabled
UART
1
1
PAR
0
0
Clock
PAR
synchronous
disabled
type
page 157
f o
3
6
4
Clock
synchronous type
UART
(7 bits)
UART
(8 bits)
UART(7 bits)
0
0
1
1
Clock
UART
synchronous type
(9 bits)
UART
(8 bits)
UART
(9 bits)
0
D8
D7 D6 D5
Logic reverse circuit + MSB/LSB conversion circuit
Data bus high-order bits
Data bus low-order bits
Logic reverse circuit + MSB/LSB conversion circuit
D8
D7 D6 D5
UART
(8 bits)
UART
(9 bits)
UART
Clock
synchronous type
(9 bits)
1
1
0
0
UART
UART(7 bits)
(7 bits)
Error signal output
UART
disable
(8 bits)
0
Clock
synchronous type
Error signal
output circuit
UiERE
1
Error signal output
enable
UARTi receive register
D4 D3
D2 D1 D0
D4 D3 D2
D1 D0
UARTi transmit register
IOPOL
No reverse
0
TXD data
reverse circuit
1
Reverse
17. Serial I/O
UiRB register
UiTB register
TXDi
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