Renesas M16C/62P Hardware Manual page 98

M16C/62P Group (M16C/62P, M16C/62PT)
Table 10.7 Allowed Transition and Setting
High-Speed Mode,
Middle-Speed Mode
(2)
Low-Speed Mode
Low Power Dissipation
Mode
(2)
PLL Operation Mode
On-chip Oscillator Mode
On-chip Oscillator
Low Power Dissipation
Mode
Stop Mode
Wait Mode
NOTES :
1. Avoid making a transition when the CM21 bit is set in to "1" (oscillation stop, re-oscillation detection function enabled).
Set the CM21 bit to "0" (oscillation stop, re-oscillation detection function disabled) before transiting.
2. On-chip oscillator clock oscillates and stops in low-speed mode. In this mode, the on-chip oscillator can be used as peripheral function clock.
Sub clock oscillates and stops in PLL operation mode. In this mode, sub clock can be used as peripheral function clock.
3. PLL operation mode can only be entered from and changed to high-speed mode.
4. Set the CM06 bit to "1" (division by 8 mode) before transiting from on-chip oscillator mode to high- or middle-speed mode.
5. When exiting stop mode, the CM06 bit is set to "1" (division by 8 mode).
6. If the CM05 bit set to "1" (main clock stop), then the CM06 bit is set to "1" (division by 8 mode).
7. A transition can be made only when sub clock is oscillating.
8. State transitions within the same mode (divide-by-n values changed or subclock oscillation turned on or off) are shown in the table below.
Sub Clock Oscillating
No Divided
Division by 2
(4)
No Division
(3)
Divided by 2
(3) (4)
Divided by 4
(3) (4)
Divided by 8
(3) (4)
Divided by 16
(2) --
No division
Divided by 2 -- (2)
-- --
Divided by 4
-- --
Divided by 8
-- --
Divided by 16
9. ( ) : setting method. See the following table.
Setting
(1)
CM04 = 0 Sub clock turned off
(2)
CM04 = 1 Sub clock oscillating
CM06 = 0,
(3)
CPU clock no division mode
CM17 = 0 , CM16 = 0
CM06 = 0,
(4) CPU clock division by 2 mode
CM17 = 0 , CM16 = 1
CM06 = 0,
(5) CPU clock division by 4 mode
CM17 = 1 , CM16 = 0
CM06 = 0,
(6) CPU clock division by 16 mode
CM17 = 1 , CM16 = 1
(7)
CM06 = 1 CPU clock division by 8 mode
Main clock, PLL clock,
(8)
CM07 = 0
or on-chip oscillator clock selected
(9)
CM07 = 1 Sub clock selected
(10)
CM05 = 0 Main clock oscillating
(11) CM05 = 1 Main clock turned off
PLC07 = 0,
(12)
Main clock selected
CM11 = 0
PLC07 = 1,
(13) PLL clock selected
CM11 = 1
(14)
CM21 = 0 Main clock or PLL clock selected
(15) CM21 = 1 On-chip oscillator clock selected
(16)
CM10 = 1 Transition to stop mode
(17)
Wait Instruction Transition to wait mode
(18) Exit stop mode or wait mode
Hardware Interrupt
R e . v 2 3 . 0 S e p 0 , 1 2 0 0 4
R E J 0 9 B 0 1 8 5 0 - 2 3 0 Z
High-Speed Mode, Low Power
(2)
Low-Speed Mode
Middle-Speed Mode Dissipation Mode
(NOTE 7)
(9)
(NOTE 8)
(11)
(8)
-- (10)
(NOTE 3)
(12)
--
(NOTE 4)
(14)
--
-- --
(NOTE 5)
(18)
(18) (18)
(18) (18) (18)
Divided Divided Divided No Divided
by 4 by 8 by 16 Division by 2
(5) (7) (6) (1)
(5) (7) (6) --
(7) (6) --
(5) (6) --
(5) (7) --
-- -- --
-- -- -- (3)
(2) -- -- (3)
-- (2) -- (3)
-- -- (2) (3)
Operation
page 84
f o 3 6 4
State after transition
PLL Operation On-chip Oscillator
(2)
Mode Mode
(NOTE 3)
(13)
-- (15)
(NOTE 1,6)
--
--
--
-- -- (NOTE 8)
-- -- (10)
(18)
--
-- (18)
Sub Clock Turned Off
Divided Divided Divided
by 4 by 8 by 16
-- -- -- --
(1) -- -- --
-- (1) -- --
-- -- (1) --
-- -- -- (1)
(4) (5) (7) (6)
(5) (7) (6)
(4) (7) (6)
(4) (5) (6)
(4) (5) (7)
--: Cannot transit
CM04, CM05, CM06, CM07 : Bits in CM0 register
CM10, CM11, CM16, CM17 : Bits in CM1 register
CM20, CM21 : Bits in CM2 register
PLC07 : Bit in PLC0 register
10. Clock Generating Circuit
On-chip Oscillator
Low Power Stop Mode
Dissipation Mode
(16) (NOTE 1)
--
(16) (NOTE 1)
-- --
(16) (NOTE 1)
-- --
-- -- --
(NOTE 1) (NOTE 1)
(11) (16)
(16) (NOTE 1)
(NOTE 8)
(NOTE 5)
(18) (NOTE 5)
(18) --
Wait Mode
(17)
(17)
(17)
--
(17)
(17)
--
--: Cannot transit