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M16C/62P Group (M16C/62P, M16C/62PT)
17.1.4 Special Mode 2
Multiple slaves can be serially communicated from one master. Transfer clock polarity and phase are
selectable. Table 17.15 lists the specifications of Special Mode 2. Table 17.16 lists the registers used in
Special Mode 2 and the register values set. Figure 17.25 shows communication control example for
Special Mode 2.
Table 17.15 Special Mode 2 Specifications
Item
Transfer Data Format
Transfer Clock
Transmit/Receive Control
Transmission Start Condition Before transmission can start, the following requirements must be met
Reception Start Condition
Interrupt Request
Generation Timing
Error Detection
Select Function
NOTES:
1. When an external clock is selected, the conditions must be met while if the CKPOL bit in the UiC0 register = 0
(transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the
external clock is in the high state; if the CKPOL bit = 1 (transmit data output at the rising edge and the receive
data taken in at the falling edge of the transfer clock), the external clock is in the low state.
2. If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit in the SiRIC register does
not change.
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
• Transfer data length: 8 bits
• Master mode
CKDIR bit in UiMR(i=0 to 2) register = 0 (internal clock) : fj/ 2(n+1)
fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of UiBRG register
• Slave mode
CKDIR bit = 1 (external clock selected) : Input from CLKi pin
Controlled by input/output ports
• The TE bit in UiC1 register= 1 (transmission enabled)
• The TI bit in UiC1 register = 0 (data present in UiTB register)
Before reception can start, the following requirements must be met
• The RE bit in UiC1 register= 1 (reception enabled)
• The TE bit in UiC1 register= 1 (transmission enabled)
• The TI bit in UiC1 register= 0 (data present in the UiTB register)
For transmission, one of the following conditions can be selected
• The UiIRS bit in UiC1 register = 0 (transmit buffer empty): when transferring data
from the UiTB register to the UARTi transmit register (at start of transmission)
• The UiIRS bit =1 (transfer completed): when the serial I/O finished sending data from
the UARTi transmit register
For reception
• When transferring data from the UARTi receive register to the UiRB register (at
completion of reception)
Overrun error (2)
This error occurs if the serial I/O started receiving the next data before reading the
UiRB register and received the 7th bit of the next data
• Clock phase setting
Selectable from four combinations of transfer clock polarities and phases
page 190
f o
3
6
4
Specification
17. Serial I/O
00h to FFh
(1)
(1)
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