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M16C/62P Group (M16C/62P, M16C/62PT)
24.9.1.3 Reception
In operating the clock-synchronous serial I/O, operating a transmitter generates a shift clock. Fix
settings for transmission even when using the device only for reception. Dummy data is output to the
outside from the TXDi pin when receiving data.
When an internal clock is selected, set the TE bit in the UiC1 register (i = 0 to 2) to 1 (transmission
enabled) and write dummy data to the UiTB register, and the shift clock will thereby be generated.
When an external clock is selected, set the TE bit to 1 and write dummy data to the UiTB register, and
the shift clock will be generated when the external clock is fed to the CLKi input pin.
When successively receiving data, if all bits of the next receive data are prepared in the UARTi receive
register while the RE bit in the UiC1 register (i = 0 to 2) = 1 (data present in the UiRB register), an
overrun error occurs and the OER bit in the UiRB register is set to "1" (overrun error occurred). In this
case, because the content of the UiRB register is indeterminate, a corrective measure must be taken
by programs on the transmit and receive sides so that the valid data before the overrun error occurred
will be retransmitted. Note that when an overrun error occurred, the IR bit in the SiRIC register does
not change state.
To receive data in succession, set dummy data in the lower-order byte of the UiTB register every time
reception is made.
When an external clock is selected, the conditions must be met while if the CKPOL bit = 0, the external
clock is in the high state; if the CKPOL bit = 1, the external clock is in the low state.
• The RE bit in the UiC1 register= 1 (reception enabled)
• The TE bit in the UiC1 register= 1 (transmission enabled)
• The TI bit in the UiC1 register= 0 (data present in the UiTB register)
R
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2
3 .
0
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0
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0
0
4
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0
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B
0
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8
5
0 -
2
3
0
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page 345
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3
6
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24. Usage Precaution
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