Renesas M16C/62P Hardware Manual page 63

M16C/62P Group (M16C/62P, M16C/62PT)
8.2.4 Read and Write Signals
When the data bus is 16 bits wide, the read and write signals can be chosen to be a combination of RD,
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BHE and WR or a combination of RD, WRL and WRH by using the PM02 bit in the PM0 register. When
the data bus is 8 bits wide, use a combination of RD, WR and BHE.
Table 8.3 shows the operation of RD, WRL, and WRH signals. Table 8.4 shows the operation of opera-
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tion of RD, WR, and BHE signals.
Table 8.3 Operation of RD, WRL and WRH Signals
Data Bus Width
16-bit
( BYTE pin
input = L)
Table 8.4 Operation of RD, WR and BHE Signals
Data Bus Width
16-bit
(BYTE pin
input = L)
8-bit (BYTE pin
input = H)
8.2.5 ALE Signal
The ALE signal latches the address when accessing the multiplex bus space. Latch the address when the
ALE signal falls.
When BYTE Pin Input = H
ALE
A0/D0 to A7/D7
A8 to A19
NOTES :
1. If the entire CS space is assigned a multiplexed bus, these pins function as I/O ports.
Figure 8.3 ALE Signal, Address Bus, Data Bus
R e . v 2 3 . 0 S e p 0 , 1 2 0 0 4
R E J 0 9 B 0 1 8 5 0 - 2 3 0 Z
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RD WRL
L H
H L
H H
H L
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RD WR BHE
H L
L H
H L
L H
H L
L H
Not used
H L
L H Not used
Address Data
(1)
Address
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f o 3 6 4
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WRH
H Read data
H Write 1 byte of data to an even address
L Write 1 byte of data to an odd address
L Write data to both even and odd addresses
A0
L H Write 1 byte of data to an odd address
L H Read 1 byte of data from an odd address
H L Write 1 byte of data to an even address
H L Read 1 byte of data from an even address
L L Write data to both even and odd addresses
L L Read data from both even and odd addresses
H or L Write 1 byte of data
H or L Read 1 byte of data
When BYTE Pin Input = L
ALE
A0
A1/D0 to A8/D7
A9 to A19
Status of External Data Bus
Status of External Data Bus
Address
Address Data
Address
8. Bus
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