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M16C/62P Group (M16C/62P, M16C/62PT)
12.9 Address Match Interrupt
An address match interrupt request is generated immediately before executing the instruction at the ad-
dress indicated by the RMADi register (i=0 to 3). Set the start address of any instruction in the RMADi
register. Use the AIER0 and AIER1 bits in the AIER register and the AIER20 and AIER21 bits in the AIER2
register to enable or disable the interrupt. Note that the address match interrupt is unaffected by the I flag
and IPL. For address match interrupts, the value of the PC that is saved to the stack area varies depending
on the instruction being executed (refer to 12.5.7 Saving Registers).
(The value of the PC that is saved to the stack area is not the correct return address.) Therefore, follow one
of the methods described below to return from the address match interrupt.
• Rewrite the content of the stack and then use the REIT instruction to return.
• Restore the stack to its previous state before the interrupt request was accepted by using the POP or
similar other instruction and then use a jump instruction to return.
Table 12.6 shows the value of the PC that is saved to the stack area when an address match interrupt
request is accepted.
Note that when using the external bus in 8 bits width, no address match interrupts can be used for external
areas.
Figure 12.12 shows the AIER, AIER2, and RMAD0 to RMAD3 registers.
Table 12.6 Value of the PC that is saved to the stack area when an address match interrupt
request is accepted.
Instruction at the Address Indicated by the RMADi Register
• 16-bit op-code instruction
• Instruction shown below among 8-bit operation code instructions
ADD.B:S
#IMM8,dest
OR.B:S
#IMM8,dest
STNZ.B:S
#IMM8,dest
CMP.B:S
#IMM8,dest
JMPS
#IMM8
MOV.B:S
#IMM,dest (However, dest=A0 or A1)
Instructions other than the above
Value of the PC that is saved to the stack area : Refer to 12.5.7 Saving Registers.
Table 12.7 Relationship Between Address Match Interrupt Sources and Associated Registers
Address Match Interrupt sources Address Match Interrupt Enable Bit Address Match Interrupt Register
Address Match Interrupt 0
Address Match Interrupt 1
Address Match Interrupt 2
Address Match Interrupt 3
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
SUB.B:S
#IMM8,dest
MOV.B:S
#IMM8,dest
STZX.B:S
#IMM81,#IMM82,dest
PUSHM
src
JSRS
#IMM8
AIER0
AIER1
AIER20
AIER21
page 105
f o
3
6
4
AND.B:S
#IMM8,dest
STZ.B:S
#IMM8,dest
POPM dest
RMAD0
RMAD1
RMAD2
RMAD3
12. Interrupt
Value of the PC that is
saved to the stack area
The address
indicated by the
RMADi register +2
The address
indicated by the
RMADi register +1
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