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M16C/62P Group (M16C/62P, M16C/62PT)
6.1 Voltage Down Detection Interrupt
If the D40 bit in the D4INT register is set to "1" (voltage down detection interrupt enabled), the voltage down
detection interrupt request is generated when the voltage applied to the VCC1 pin is above or below Vdet4.
The voltage down detection interrupt shares the same interrupt vector with the watchdog timer interrupt and
oscillation stop, re-oscillation detection interrupt.
Set the D41 bit in the D4INT register to "1" (enabled) to use the voltage down detection interrupt to exit stop
mode.
The D42 bit in the D4INT register is set to "1" as soon as the voltage applied to the VCC1 pin reaches Vdet4
due to the voltage rise and voltage drop. When the D42 bit changes "0" to "1", the voltage down detection
interrupt request is generated. Set the D42 bit to "0" by program. However, when the D41 bit is set to "1"
and the microcomputer is in stop mode, the voltage down detection interrupt request is generated regard-
less of the D42 bit state if the voltage applied to the VCC1 pin is detected to be above Vdet4. The micro-
computer then exits stop mode.
Table 6.1 shows how the voltage down detection interrupt request is generated.
The DF1 to DF0 bits in the D4INT register determine the sampling period that detects the voltage applied to
the VCC1 pin reaches Vdet4. Table 6.2 shows the sampling periods.
Table 6.1 Voltage Down Detection Interrupt Request Generation Conditions
Operation Mode
VC27 Bit
Normal
Operation
Mode
(1)
Wait Mode
(2)
Stop Mode
(2)
NOTES:
1. The status except the wait mode and stop mode is handled as the normal mode.(Refer to 10. Clock generating circuit)
2. Refer to 6.2 Limitations on stop mode, 6.3 Limitations on wait mode.
3. An interrupt request for voltage reduction is generated a sampling time after the value of the VC13 bit has changed.
See the Figure 6.5 Voltage Down Detection Interrupt Generation Circuit Operation Example for details.
Table 6.2 Sampling Periods
CPU
Clock
DF1 to DF0=00
(MHz)
(CPU clock divided by 8)
16
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
D40 Bit
1
1
DF1 to DF0=01
(CPU clock divided by 16)
3.0
page 38
f o
3
6
4
D41 Bit
D42 Bit
0 to 1
0 to 1
1
Sampling Period (µs)
DF1 to DF0=10
(CPU clock divided by 32)
6.0
6. Voltage Detection Circuit
CM02 Bit
VC13 Bit
0 to 1
(3)
1 to 0
(3)
0 to 1
(3)
0
1 to 0
(3)
1
0 to 1
0
0 to 1
– : "0"or "1"
DF1 to DF0=11
(CPU clock divided by 64)
12.0
24.0
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