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M16C/62P Group (M16C/62P, M16C/62PT)
______
12.6 INT Interrupt
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INTi interrupt (i=0 to 5) is triggered by the edges of external inputs. The edge polarity is selected using the
IFSRi bit in the IFSR register.
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________
INT4 and INT5 share the interrupt vector and interrupt control register with SI/O3 and SI/O4, respectively.
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To use the INT4 interrupt, set the IFSR6 bit in the IFSR register to "1" (= INT4). To use the INT5 interrupt,
set the IFSR7 bit in the IFSR register to "1" (= INT5).
After modifying the IFSR6 or IFSR7 bit, clear the corresponding IR bit to "0" (= interrupt not requested)
before enabling the interrupt.
Figure 12.10 shows the IFSR and IFSR2A registers.
Interrupt Request Cause Select Register
b7
b6
b5
NOTES:
1. When setting this bit to "1" (= both edges), make sure the POL bit in the INT0IC to INT5IC
register are set to "0" (= falling edge).
2. During memory expansion and microprocessor modes, set this bit to "0" (= SI/O3, SI/O4)
3. When setting this bit to "0" (= SI/O3, SI/O4), make sure the POL bit in the S3IC and S4IC
registers are set to "0" (= falling edge).
Interrupt Request Cause Select Register 2
b7
b6
b5
NOTES :
1. Timer B3 and UART0 bus collision detection share the vector and interrupt control register. When using the
timer B3 interrupt, clear the IFSR26 bit to "0" (Timer B3). When using UART0 bus collision detection, set the
IFSR26 bit to "1".
2. Timer B4 and UART1 bus collision detection share the vector and interrupt control register. When using the
timer B4 interrupt, clear the IFSR27 bit to "0" (Timer B4). When using UART1 bus collision detection, set the
IFSR27 bit to "1".
Figure 12.10 IFSR Register and IFSR2A Register
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
b4
b3
b2
b1
b0
Symbol
IFSR
Bit Symbol
IFSR0
INT0 Interrupt Polarity
Switching Bit
IFSR1
INT1 Interrupt Polarity
Switching Bit
IFSR2
INT2 Interrupt Polarity
Switching Bit
IFSR3
INT3 Interrupt Polarity
Switching Bit
IFSR4
INT4 Interrupt Polarity
Switching Bit
IFSR5
INT5 Interrupt Polarity
Switching Bit
IFSR6
Interrupt Request Cause
Select Bit
IFSR7
Interrupt Request Cause
Select Bit
b4
b3
b2
b1
b0
Symbol
IFSR2A
Bit Symbol
(b5-b0)
IFSR26
Interrupt Request Cause
Select Bit
IFSR27
Interrupt Request Cause
Select Bit
page 103
f o
3
6
4
________
Address
After Reset
035Fh
Bit Name
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : SI/O3
(2)
1 : INT4
0 : SI/O4
(2)
1 : INT5
Address
After Reset
035Eh
00XXXXXXb
Bit Name
Nothing is assigned. When write, set to "0".
When read, their contents are indeterminate.
(1)
0 : Timer B4
1 : UART1 bus collision
(2)
________
00h
Function
RW
RW
(1)
RW
(1)
RW
(1)
RW
(1)
RW
(1)
RW
(1)
(3)
RW
(3)
RW
Function
RW
0 : Timer B3
1 : UART0 bus collision
RW
detection
RW
detection
12. Interrupt
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