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M16C/62P Group (M16C/62P, M16C/62PT)
24.8.1.2 Timer A (Event Counter Mode)
The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i
= 0 to 4) register, the TAi register, the UDF register, the ONSF register TAZIE, TA0TGL and TA0TGH
bits and the TRGSR register before setting the TAiS bit in the TABSR register to "1" (count starts).
Always make sure the TAiMR register, the UDF register, the TAZIE, TA0TGL and TA0TGH bits in the
ONSF register and the TRGSR register are modified while the TAiS bit remains "0" (count stops)
regardless whether after reset or not.
While counting is in progress, the counter value can be read out at any time by reading the TAi
register. However, "FFFFh" can be read in underflow, while reloading, and "0000h" in overflow. When
setting TAi register to a value during a counter stop, the setting value can be read before a counter
starts counting. Also, if the counter is read before it starts counting after a value is set in the TAi
register while not counting, the set value is read.
If a low-level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC register = 1 (three-
phase output forcible cutoff by input on NMI pin enabled), the TA1OUT, TA2OUT and TA4OUT pins
go to a high-impedance state.
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
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page 337
f o
3
6
4
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24. Usage Precaution
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