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M16C/62P Group (M16C/62P, M16C/62PT)
Oscillation Stop Detection Register
b7
b6
b5
b4
b3
0 0
NOTES:
1. Write to this register after setting the PRC0 bit in the PRCR register to "1" (write enable).
2. When the CM20 bit is "1" (oscillation stop, re-oscillation detection function enabled), the CM27 bit is "1"
(oscillation stop, re-oscillation detection interrupt), and the CPU clock source is the main clock, the
CM21 bit is set to "1" (on-chip oscillator clock) if the main clock stop is detected.
3. If the CM20 bit is "1" and the CM23 bit is "1" (main clock turned off), do not set the CM21 bit to "0".
4. This flag is set to "1" when the main clock is detected to have stopped and when the main clock is
detected to have restarted oscillating. When this flag changes state from "0" to "1," an oscillation stop or
an oscillation restart detection interrupt is generated. Use this flag in an interrupt routine to discriminate
the causes of interrupts between the oscillation stop and oscillation restart detection interrupts and the
watchdog timer interrupt. The flag is cleared to "0" by writing a "0" in a program. (Writing a "1" has no
effect. Nor is it cleared to "0" by an oscillation stop or an oscillation restart detection interrupt request
acknowledged.)
If when the CM22 bit = 1 an oscillation stoppage or an oscillation restart is detected, no oscillation
stop and oscillation restart detection interrupts are generated.
5. Read the CM23 bit in an oscillation stop, re-oscillation detection interrupt handling routine to determine
the main clock status.
6. Effective when the CM07 bit in the CM0 register is "0".
7. When the PM21 bit in the PM2 register is "1" (clock modification disabled), writing to the CM20 bit has no
effect.
8. Where the CM20 bit is "1" (oscillation stop, re-oscillation detection function enabled), the CM27 bit is "1"
(oscillation stop, re-oscillation detection interrupt), and the CM11 bit is "1" (the CPU clock source is PLL
clock), the CM21 bit remains unchanged even when main clock stop is detected. If the CM22 bit is "0"
under these conditions, oscillation stop, re-oscillation detection interrupt occur at main clock stop
detection; it is, therefore, necessary to set the CM21 bit to "1" (on-chip oscillator clock) inside the interrupt
routine.
9. Set the CM20 bit to "0" (disable) before entering stop mode. After exiting stop mode, set the CM20 bit
back to "1" (enable).
10. Set the CM20 bit to "0" (disable) before setting the CM05 bit in the CM0 register.
11. The CM20, CM21 and CM27 bits do not change at oscillation stop detection reset.
12. When the CM21 bit = 0 (on-chip oscillator turned off) and the CM05 bit = 1 (main clock turned off), the
CM06 bit is fixed to "1" (divide-by-8 mode) and the CM15 bit is fixed to "1" (drive capability High).
Figure 10.4 CM2 Register
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
b2
b1
b0
Symbol
CM2
Bit Symbol
Oscillation Stop,
CM20
Re-Oscillation Detection
Bit
System Clock
CM21
Select Bit 2
(2, 3, 6, 8, 11, 12)
Oscillation Stop,
CM22
Re-Oscillation Detection
Flag
XIN Monitor Flag
CM23
Reserved Bit
(b5-b4)
Nothing is assigned. When write, set to "0". When read, its
(b6)
content is indeterminate.
Operation Select Bit
CM27
(when an oscillation stop,
re-oscillation is detected)
(11)
page 69
f o
3
6
4
(1)
Address
After Reset
000Ch
Bit Name
0: Oscillation stop, re-oscillation
1: Oscillation stop, re-oscillation
(7, 9, 10, 11)
0: Main clock or PLL clock
1: On-chip oscillator clock
0: Main clock stop, re-oscillation
(4)
1: Main clock stop, re-oscillation
0: Main clock oscillating
(5)
1: Main clock turned off
Set to "0"
0: Oscillation stop detection reset
1: Oscillation stop, re-oscillation
10. Clock Generating Circuit
(11)
0X000000b
Function
detection function disabled
detection function enabled
(On-chip oscillator oscillating)
not detected
detected
detection interrupt
RW
RW
RW
RW
RO
RW
RW
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