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M16C/62P Group (M16C/62P, M16C/62PT)
(1) Separate Bus, 3-Wait Setting
(2) Multiplexed Bus, 1- or 2-Wait Setting
(3) Multiplexed Bus, 3-Wait Setting
NOTES :
1. These example timing charts indicate bus cycle length. After this bus cycle sometimes come read and write cycles in
succession.
Figure 8.8 Typical Bus Timings Using Software Wait (2)
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
Bus cycle
BCLK
Write signal
Read signal
Data bus
Address bus
CS
Bus cycle
BCLK
Write signal
Read signal
ALE
Address
Address bus
Address bus/
Address
Data output
Data bus
CS
Bus cycle
BCLK
Write signal
Read signal
ALE
Address bus
Address bus/
Address
Data bus
CS
page 56
f o
3
6
4
(1)
Output
Address
(1)
Address
(1)
Address
Data output
(1)
Bus cycle
Address
(1)
Bus cycle
Address
Input
(1)
Bus cycle
Address
Address
8. Bus
Input
Input
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