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M16C/62P Group (M16C/62P, M16C/62PT)
Table17.12 Registers to Be Used and Settings in I
Register
Bit
UiSMR4 STAREQ
RSTAREQ
STPREQ
STSPSEL
ACKD
ACKC
SCLHI
SWC9
IFSR2A IFSR26, ISFR27
UCON
U0IRS, U1IRS
2 to 7
i=0 to 2
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
Master
Set this bit to "1" to generate start
condition
Set this bit to "1" to generate restart
condition
Set this bit to "1" to generate stop
condition
Set this bit to "1" to output each condition Set to "0"
Select ACK or NACK
Set this bit to "1" to output ACK data
Set this bit to "1" to have SCLi output
stopped when stop condition is detected
Set to "0"
Set to "1"
Invalid
Set to "0"
page 183
f o
3
6
4
2
C Mode (2) (Continued)
Function
Set to "0"
Set to "0"
Set to "0"
Select ACK or NACK
Set this bit to "1" to output ACK data
Set to "0"
Set this bit to "1" to set the SCLi to "L"
hold at the falling edge of the 9th bit of
clock
Set to "1"
Invalid
Set to "0"
17. Serial I/O
Slave
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