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M16C/62P Group (M16C/62P, M16C/62PT)
14. DMAC
The DMAC (Direct Memory Access Controller) allows data to be transferred without the CPU intervention.
Two DMAC channels are included. Each time a DMA request occurs, the DMAC transfers one (8 or 16-bit)
data from the source address to the destination address. The DMAC uses the same data bus as used by
the CPU. Because the DMAC has higher priority of bus control than the CPU and because it makes use of
a cycle steal method, it can transfer one word (16 bits) or one byte (8 bits) of data within a very short time
after a DMA request is generated. Figure 14.1 shows the block diagram of the DMAC. Table 14.1 shows
the DMAC specifications. Figures 14.2 to 14.4 show the DMAC-related registers.
DMA0 transfer counter reload register TCR0 (16)
DMA0 transfer counter TCR0 (16)
DMA1 transfer counter reload register TCR1 (16)
DMA1 transfer counter TCR1 (16)
Figure 14.1 DMAC Block Diagram
A DMA request is generated by a write to the DSR bit in the DMiSL register (i = 0 to 1), as well as by an
interrupt request which is generated by any function specified by the DMS and DSEL3 to DSEL0 bits in the
DMiSL register. However, unlike in the case of interrupt requests, DMA requests are not affected by the I
flag and the interrupt control register, so that even when interrupt requests are disabled and no interrupt
request can be accepted, DMA requests are always accepted. Furthermore, because the DMAC does not
affect interrupts, the IR bit in the interrupt control register does not change state due to a DMA transfer.
A data transfer is initiated each time a DMA request is generated when the DMAE bit in the DMiCON
register = 1 (DMA enabled). However, if the cycle in which a DMA request is generated is faster than the
DMA transfer cycle, the number of transfer requests generated and the number of times data is transferred
may not match. Refer to 14.4 DMA Requests for details.
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
(addresses 0029h, 0028h)
(addresses 0039h, 0038h)
Data bus low-order bits
Data bus high-order bits
page 110
f o
3
6
4
Address bus
DMA0 source pointer SAR0(20)
DMA0 destination pointer DAR0 (20)
DMA0 forward address pointer (20)
DMA1 source pointer SAR1 (20)
DMA1 destination pointer DAR1 (20)
DMA1 forward address pointer (20)
DMA latch high-order bits
NOTES :
1. Pointer is incremented by a DMA request.
(addresses 0022h to 0020h)
(addresses 0026h to 0024h)
(1)
(addresses 0032h to 0030h)
(addresses 0036h to 0034h)
(1)
DMA latch low-order bits
14. DMAC
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