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M16C/62P Group (M16C/62P, M16C/62PT)
15.2.2 Event Counter Mode
In event counter mode, the timer counts pulses from an external device or overflows and underflows of
other timers (see Table 15.7). Figure 15.19 shows TBiMR register in event counter mode.
Table 15.7 Specifications in Event Counter Mode
Item
Count Source
Count Operation
Divide Ratio
Count Start Condition
Count Stop Condition
Interrupt Request Generation Timing Timer underflow
TBiIN Pin Function
Read from Timer
Write to Timer
NOTES:
1. The TB0S to TB2S bits are assigned to the TABSR register bit 5 to bit 7, and the TB3S to TB5S bits
are assigned to the TBSR register bit 5 to bit 7.
Timer Bi Mode Register (i=0 to 5)
b7
b6
b5
b4
b3
NOTES:
1. Effective when the TCK1 bit = 0 (input from TBiIN pin). If the TCK1 bit = 1 (TBj overflow or underflow), these
bits can be set to "0" or "1".
2. The port direction bit for the TBiIN pin must be set to "0" (= input mode).
Figure 15.19 TBiMR Register in Event Counter Mode
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
• External signals input to TBiIN pin (i=0 to 5) (effective edge can be
selected in program)
• Timer Bj overflow or underflow (j=i-1, except j=2 if i=0, j=5 if i=3)
• Down-count
• When the timer underflows, it reloads the reload register contents and
continues counting
1/(n+1)
Set TBiS bit
Set TBiS bit to "0" (= stop counting)
Count source input
Count value can be read by reading TBi register
• When not counting and until the 1st count source is input after counting start
Value written to TBi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TBi register is written to only reload register
(Transferred to counter when reloaded next)
Symbol
b2
b1
b0
TB0MR to TB2MR
0 1
TB3MR to TB5MR
Bit Symbol
TMOD0
Operation Mode Select Bit
TMOD1
MR0
Count Polarity Select
Bit
(1)
MR1
TB0MR, TB3MR registers
MR2
Set to "0" in timer mode
TB1MR, TB2MR, TB4MR, TB5MR registers
Nothing is assigned. When write, set to "0". When read, its
content is indeterminate.
When write in event counter mode, set to "0". When read in event
MR3
counter mode, its content is indeterminate.
Has no effect in event counter mode.
TCK0
Can be set to "0" or "1".
Event Clock Select
TCK1
page 141
f o
3
6
4
Specification
n: set value of TBi register
(1)
to "1" (= start counting)
Address
After Reset
039Bh to 039Dh
00XX0000b
035Bh to 035Dh
00XX0000b
Bit Name
b1 b0
0 1 : Event counter mode
b3 b2
0 0 : Counts falling edges of external
signal
0 1 : Counts rising edges of external
signal
1 0 : Counts falling and rising edges
external signal
1 1 : Do not set to this value
0 : Input from TBiIN pin
1 : TBj overflow or underflow
(j = i – 1, except j = 2 if i = 0,
0000h to FFFFh
Function
RW
RW
RW
RW
RW
RW
RO
RW
(2)
RW
j = 5 if i = 3)
15. Timers
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