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M16C/62P Group (M16C/62P, M16C/62PT)
24.10 A/D Converter
Set ADCON0 (except bit 6), ADCON1 and ADCON2 registers when A/D conversion is stopped (before a
trigger occurs).
When the VCUT bit in the ADCON1 register is changed from "0" (Vref not connected) to "1" (Vref con-
nected), start A/D conversion after passing 1 µs or longer.
To prevent noise-induced device malfunction or latch-up, as well as to reduce conversion errors, insert
capacitors between the AVCC, VREF, and analog input pins (ANi(i=0 to 7), AN0_i, AN2_i) each and the
AVSS pin. Similarly, insert a capacitor between the VCC1 pin and the VSS pin. Figure 24.4 is an example
connection of each pin.
Make sure the port direction bits for those pins that are used as analog inputs are set to "0" (input mode).
Also, if the TGR bit in the ADCON0 register = 1 (external trigger), make sure the port direction bit for the
____________
ADTRG pin is set to "0" (input mode).
When using key input interrupts, do not use any of the four AN4 to AN7 pins as analog inputs. (A key input
interrupt request is generated when the A/D input voltage goes low.)
The ØAD frequency must be 12MHz or less. Without sample-and-hold function, limit the ØAD frequency to
250kHz or more. With the sample and hold function, limit the ØAD frequency to 1MHz or more.
When changing an A/D operation mode, select analog input pin again in the CH2 to CH0 bits in the
ADCON0 register and the SCAN1 to SCAN0 bits in the ADCON1 register.
Figure 24.4 Use of capacitors to reduce noise
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
Microcomputer
VCC1
VCC1
C4
VSS
VCC2
VCC2
C5
VSS
ANi: ANi, AN0_i, and AN2_i (i=0 to 7)
NOTES :
1. C1≥0.47µF, C2≥0.47µF, C3≥100pF, C4≥0.1µF, C5≥0.1µF ( reference)
2. Use thick and shortest possible wiring to connect capacitors.
page 348
f o
3
6
4
AVCC
VREF
C2
C1
AVSS
C3
ANi
24. Usage Precaution
VCC1
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