Table of Contents
Advertisement
M16C/62P Group (M16C/62P, M16C/62PT)
17.1.1.5 Serial Data Logic Switching Function
When the UiLCH bit in the UiC1 register (i = 0 to 2) = 1 (reverse), the data written to the UiTB register
has its logic reversed before being transmitted. Similarly, the received data has its logic reversed
when read from the UiRB register. Figure 17.12 shows serial data logic.
(1) When the UiLCH bit in the UiC1 register = 0 (no reverse)
Transfer clock
(no reverse)
(2) When the UiLCH bit = 1 (reverse)
Transfer clock
(reverse)
NOTES :
1. This applies to the case where the CKPOL bit in the UiC0 register = 0
i = 0 to 2
Figure 17.12 Serial Data Logic Switching
17.1.1.6 Transfer Clock Output From Multiple Pins (UART1)
Use the CLKMD1 to CLKMD0 bits in the UCON register to select one of the two transfer clock output
pins (see Figure 17.13). This function can be used when the selected transfer clock for UART1 is an
internal clock.
Microcomputer
TXD1 (P6_7)
CLKS1 (P6_4)
CLK1 (P6_5)
NOTES :
1. This applies to the case where the CKDIR bit in the U1MR register = 0
(internal clock) and the CLKMD1 bit in the UCON register = 1
(transfer clock output from multiple pins).
Figure 17.13 Transfer Clock Output From Multiple Pins
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
"H"
"L"
TXDi
"H"
D0
D1
"L"
"H"
"L"
TXDi
"H"
D0
D1
"L"
(transmit data output at the falling edge and the receive data taken
in at the rising edge of the transfer clock) and the UFORM bit = 0
(LSB first).
Transfer enabled
when the CLKMD0
bit in the UCON
register = 0
page 170
f o
3
6
4
D2
D3
D4
D5
D6
D2
D3
D4
D5
D6
IN
CLK
Transfer enabled
when the
CLKMD0 bit = 1
D7
D7
IN
CLK
17. Serial I/O
Advertisement
Table of Contents
