Renesas M16C/62P Hardware Manual page 174

M16C/62P Group (M16C/62P, M16C/62PT)
UARTi Transmit/Receive Control Register 1 (i=0, 1)
b7 b6 b5 b4 b3 b2 b1
NOTES:
1. The UiLCH bit is enabled when the SMD2 to SMD0 bits in the UiMR register are set to "001b" (clock synchronous serial I/O
mode), "100b" (UART mode, 7-bit transfer data), or "101b" (UART mode, 8-bit transfer data).
Set this bit to "0" when the SMD2 to SMD0 bits are set to "010b" (I
UART2 Transmit/Receive Control Register 1
b7 b6 b5 b4 b3 b2
NOTES:
1. The U2LCH bit is enabled when the SMD2 to SMD0 bits in the U2MR registerare set to "001b" (clock synchronous serial I/O
mode), "100b" (UART mode, 7-bit transfer data), or "101b" (UART mode, 8-bit transfer data).
Set this bit to "0" when the SMD2 to SMD0 bits are set to "010b" (I
Figure 17.7 U0C1 to U2C1 Registers
R e . v 2 3 . 0 S e p 0 , 1 2 0 0 4
R E J 0 9 B 0 1 8 5 0 - 2 3 0 Z
b0
Symbol
U0C1, U1C1
Bit
Bit Name
Symbol
TE Transmit Enable Bit
TI Transmit Buffer
Empty Flag
RE Receive Enable Bit
RI Receive Complete Flag
Nothing is assigned.
(b5-b4)
When write, set "0". When read, these contents are indeterminate.
Data Logic Select Bit
UiLCH
UiERE
Error Signal Output
Enable Bit
b1 b0
Symbol
U2C1
Bit
Bit Name
Symbol
TE Transmit Enable bit
Transmit Buffer
TI
Empty Flag
RE Receive Enable Bit
RI Receive Complete Flag
U2IRS UART2 Transmit Interrupt
Cause Select Bit
U2RRM UART2 Continuous
Receive Mode Enable Bit
U2LCH
Data Logic Select Bit
U2ERE Error Signal Output
Enable Bit
page 160
f o 3 6 4
Address After Reset
03A5h, 03ADh 00XX0010b
0 : Transmission disabled
1 : Transmission enabled
0 : Data present in UiTB register
1 : No data present in UiTB register
0 : Reception disabled
1 : Reception enabled
0 : No data present in UiRB register
1 : Data present in UiRB register
(1)
0 : No reverse
1 : Reverse
0 : Output disabled
1 : Output enabled
2
C mode) or "110b" (UART mode, 9-bit transfer data).
Address After Reset
037Dh 00000010b
0 : Transmission disabled
1 : Transmission enabled
0 : Data present in U2TB register
1 : No data present in U2TB register
0 : Reception disabled
1 : Reception enabled
0 : No data present in U2RB register
1 : Data present in U2RB register
0 : Transmit buffer empty (TI = 1)
1 : Transmit is completed (TXEPT = 1)
0 : Continuous receive mode disabled
1 : Continuous receive mode enabled
(1) 0 : No reverse
1 : Reverse
0 : Output disabled
1 : Output enabled
2
C mode) or "110b" (UART mode, 9-bit transfer data).
17. Serial I/O
Function
Function
RW
RW
RO
RW
RO
RW
RW
RW
RW
RO
RW
RO
RW
RW
RW
RW