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M16C/62P Group (M16C/62P, M16C/62PT)
Memory Expansion Mode, Microprocessor Mode
(
For 1- or 2-wait setting, external area access and multiplex bus selection
Read timing
BCLK
CSi
ADi
/DBi
ADi
BHE
ALE
RD
Write timing
BCLK
CSi
ADi
/DBi
ADi
BHE
ALE
WR,WRL,
WRH
1
t
cyc=
f(BCLK)
Measuring conditions
• V
=V
CC1
CC2
• Input timing voltage
• Output timing voltage : V
Figure 23.10 Timing Diagram (8)
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
t
d(BCLK-CS)
25ns.max
t
d(AD-ALE)
(0.5 X tcyc-25)ns.min
Address
t
d(BCLK-AD)
25ns.max
t
d(BCLK-ALE)
t
h(BCLK-ALE)
25ns.max
-4ns.min
t
d(BCLK-CS)
25ns.max
Address
t
d(AD-ALE)
(0.5 X tcyc-25)ns.min
t
d(BCLK-AD)
25ns.max
t
d(BCLK-ALE)
t
h(BCLK-ALE)
25ns.max
-4ns.min
=5V
: V
=0.8V, V
=2.0V
IL
IH
=0.4V, V
OL
OH
page 294
f o
3
6
4
23. Electrical Characteristics (M16C/62P)
tcyc
t
h(ALE-AD)
(0.5 X tcyc-15)ns.min
t
dZ(RD-AD)
8ns.max
t
ac3(RD-DB)
(1.5 X tcyc-45)ns.max
t
d(AD-RD)
0ns.min
t
d(BCLK-RD)
25ns.max
tcyc
t
d(BCLK-DB)
40ns.max
Data output
t
d(DB-WR)
(1.5 X tcyc-40)ns.min
t
d(AD-WR)
0ns.min
t
d(BCLK-WR)
25ns.max
=2.4V
V
= V
CC1
CC2
)
t
h(BCLK-CS)
t
h(RD-CS)
4ns.min
(0.5 X tcyc-10)ns.min
Data input
t
h(RD-DB)
t
su(DB-RD)
0ns.min
40ns.min
t
h(BCLK-AD)
4ns.min
t
h(RD-AD)
(0.5 X tcyc-10)ns.min
t
h(BCLK-RD)
0ns.min
t
h(BCLK-CS)
t
h(WR-CS)
4ns.min
(0.5 X tcyc-10)ns.min
t
h(BCLK-DB)
4ns.min
t
h(WR-DB)
(0.5 X tcyc-10)ns.min
t
h(BCLK-AD)
4ns.min
t
h(WR-AD)
(0.5 X tcyc-10)ns.min
t
h(BCLK-WR)
0ns.min
= 5V
Address
Address
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