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M16C/62P Group (M16C/62P, M16C/62PT)
13. Watchdog Timer
The watchdog timer is the function of detecting when the program is out of control. Therefore, we recom-
mend using the watchdog timer to improve reliability of a system. The watchdog timer contains a 15-bit
counter which counts down the clock derived by dividing the CPU clock using the prescaler. Whether to
generate a watchdog timer interrupt request or apply a watchdog timer reset as an operation to be per-
formed when the watchdog timer underflows after reaching the terminal count can be selected using the
PM12 bit of PM1 register. The PM12 bit can only be set to "1" (reset). Once this bit is set to "1," it cannot be
set to "0" (watchdog timer interrupt) in a program. Refer to 5.3 Watchdog Timer Reset for the details of
watchdog timer reset.
When the main clock source is selected for CPU clock, on-chip oscillator clock, PLL clock, the divide-by-N
value for the prescaler can be chosen to be 16 or 128. If a sub-clock is selected for CPU clock, the divide-
by-N value for the prescaler is always 2 no matter how the WDC7 bit is set. The period of watchdog timer
can be calculated as given below. The period of watchdog timer is, however, subject to an error due to the
prescaler.
With main clock source chosen for CPU clock, on-chip oscillator clock, PLL clock
Watchdog timer period =
With sub-clock chosen for CPU clock
Watchdog timer period =
For example, when CPU clock = 16 MHz and the divide-by-N value for the prescaler= 16, the watchdog
timer period is approx. 32.8 ms.
The watchdog timer is initialized by writing to the WDTS register. The prescaler is initialized after reset.
Note that the watchdog timer and the prescaler both are inactive after reset, so that the watchdog timer is
activated to start counting by writing to the WDTS register.
In stop mode, wait mode and hold state, the watchdog timer and prescaler are stopped. Counting is
resumed from the held value when the modes or state are released.
Figure 13.1 shows the block diagram of the watchdog timer. Figure 13.2 shows the watchdog timer-related
registers.
CPU
clock
HOLD
Write to WDTS register
Internl RESET signal
("L" active)
CM07: Bit in CM0 register
WDC7: Bit in WDC register
PM12: Bit in PM1 register
PM22: Bit in PM2 register
Figure 13.1 Watchdog Timer Block Diagram
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
Prescaler dividing (16 or 128) X Watchdog timer count (32768)
Prescaler dividing (2) X Watchdog timer count (32768)
Prescaler
CM07 = 0
WDC7 = 0
1/16
CM07 = 0
WDC7 = 1
1/128
CM07 = 1
1/2
On-chip oscillator clock
page 107
f o
3
6
4
CPU clock
CPU clock
PM22 = 0
Watchdog timer
PM22 = 1
Set to
"7FFFh"
13. Watchdog Timer
Watchdog timer
PM12 = 0
interrupt request
PM12 = 1
Reset
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