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M16C/62P Group (M16C/62P, M16C/62PT)
Appendix 2. Differences Between M16C/62P and M16C/62A
Appendix Table 2.1 Differences in Mask ROM Version and Flash Memory Version (1)
Item
Shortest instruction
execution time
Supply voltage
I/O power supply
Package
Voltage detection
circuit
Clock Generating
Circuit
System clock
protective function
Oscillation stop,
re-oscillation detection
function
Low power
consumption
Memory area
External device
connect area
Upper address in
memory expansion
mode and
microprocessor mode
Access to SFR
Software wait to
external area
Protect
Watchdog timer
Address match
interrupt
NOTES :
1. About the details and the electric characteristics, refer to hardware manual.
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
M16C/62P
41.7ns (f(BCLK)=24MHz, VCC1=3.0 to 5.5V)
100ns (f(BCLK)=10MHz, VCC1=2.7 to 5.5V)
VCC1=3.0 to 5.5V, VCC2=3.0V to VCC1
(f(BCLK)=24MHz)
VCC1=VCC2=2.7 to 5.5V
(f(BCLK)=10MHz)
Double (VCC1, VCC2)
80-pin, 100-pin, 128-pin plastic mold QFP
Built-in
Vdet3, Vdet4 detect
Voltage down detect interrupt
Hardware reset 2
PLL, XIN, XCIN, on-chip oscillator
When placed in low power mode, a divide-
by-8 value is used for these clocks. The XIN
drive capability is set to HIGH.
Built-in
Built-in
18mA (VCC1=VCC2=5V, f(BCLK)=24MHz)
8mA
(VCC1=VCC2=3V, f(BCLK)=10MHz)
1.8µA (VCC1=VCC2=3V, f(XCIN)=32kHz,
when wait mode)
Memory area expandable
(4 Mbytes)
04000h–07FFFh(PM13=0)
08000h–0FFFFh(PM10=0)
10000h–26FFFh
28000h–7FFFFh
80000h–CFFFFh(PM13=0)
D0000h–FFFFFh(Microprocessor mode)
P4_0 to P4_3 (A16 to A19), P3_4 to P3_7
(A12 to A15) : Switchable between
address bus and I/O port
Variable (1 to 2 waits)
Variable (0 to 3 waits)
Can be set for PM0, PM1, PM2, CM0,
CM1, CM2, PLC0, INVC0, INVC1, PD9,
S3C, S4C, TB2SC, PCLKR, VCR2, D4INT
registers
Watchdog timer interrupt or watchdog
timer reset is selected
Count source protective mode is available
4
page 361
f o
3
6
4
Appendix 2. Differences Between M16C/62P and M16C/62A
62.5ns (f(XIN)=16MHz, VCC=4.2V to 5.5V)
100ns (f(XIN)=10MHz, VCC=2.7V to 5.5V
VCC=4.2V to 5.5V (f(XIN)=16MHz,
VCC=2.7V to 5.5V (f(XIN)=10MHz,
Single (VCC)
80-pin, 100-pin plastic mold QFP
None
XIN, XCIN
When placed in low power mode, the
divide-by-n value for the main clock
does not change. Nor does the XIN
drive capability change.
None
(protected by protect register)
None
32.5mA (VCC=5V, f(XIN)=16MHz)
8.5mA (VCC=3V, f(XCIN)=10MHz with
0.9µA (VCC=3V, f(XCIN)=32kHz,
1 Mbytes fixed
04000h–05FFFh(PM13=0)
06000h–CFFFFh
D0000h–FFFFFh(Microprocessor mode)
P4_0 to P4_3 (A16 to A19) : Switchable
between address bus and I/O port
A12 to A15 : No switchable
1 wait fixed
Variable (0 to 1 wait)
Can be set for PM0, PM1, CM0, CM1,
PD9, S3C, S4C registers
Watchdog timer interrupt
No count source protective mode
2
(1)
M16C/62A
with software one-wait)
without software wait)
with software one-wait)
software one-wait)
when wait mode)
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