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M16C/62P Group (M16C/62P, M16C/62PT)
Table 17. 11 Registers to Be Used and Settings in I
Register
Bit
(3)
UiTB
0 to 7
(3)
UiRB
0 to 7
8
ABT
OER
UiBRG
0 to 7
(3)
UiMR
SMD2 to SMD0
CKDIR
IOPOL
UiC0
CLK1, CLK0
CRS
TXEPT
CRD
NCH
CKPOL
UFORM
UiC1
TE
TI
RE
RI
(1)
U2IRS
(1)
U2RRM
UiLCH, UiERE
UiSMR
IICM
ABC
BBS
3 to 7
UiSMR2 IICM2
CSC
SWC
ALS
STAC
SWC2
SDHI
7
UiSMR3 0, 2, 4 and NODC Set to "0"
CKPH
DL2 to DL0
i=0 to 2
NOTES:
1. Set the bit 4 and bit 5 in the U0C1 and U1C1 register to "0". The U0IRS, U1IRS, U0RRM and U1RRM bits are in
the UCON register.
2. TXD2 pin is N channel open-drain output. No NCH bit in the U2C0 register is assigned. When write, set to "0".
3. Not all register bits are described above. Set those bits to "0" when writing to the registers in I
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
Master
Set transmission data
Reception data can be read
ACK or NACK is set in this bit
Arbitration lost detection flag
Overrun error flag
Set a transfer rate
Set to "010b"
Set to "0"
Set to "0"
Select the count source for the UiBRG
register
Invalid because CRD = 1
Transmit buffer empty flag
Set to "1"
(2)
Set to "1"
Set to "0"
Set to "1"
Set this bit to "1" to enable transmission
Transmit buffer empty flag
Set this bit to "1" to enable reception
Reception complete flag
Invalid
,
Set to "0"
Set to "1"
Select the timing at which arbitration-lost Invalid
is detected
Bus busy flag
Set to "0"
See Table 17.13 I
Set this bit to "1" to enable clock
synchronization
Set this bit to "1" to have SCLi output
fixed to "L" at the falling edge of the 9th
bit of clock
Set this bit to "1" to have SDAi output
stopped when arbitration-lost is detected
Set to "0"
Set this bit to "1" to have SCLi output
forcibly pulled low
Set this bit to "1" to disable SDAi output
Set to "0"
See Table 17.13 I
Set the amount of SDAi digital delay
page 182
f o
3
6
4
2
C Mode (1) (Continued)
Function
Set transmission data
Reception data can be read
ACK or NACK is set in this bit
Invalid
Overrun error flag
Invalid
Set to "010b"
Set to "1"
Set to "0"
Invalid
Invalid because CRD = 1
Transmit buffer empty flag
Set to "1"
Set to "1"
Set to "0"
Set to "1"
Set this bit to "1" to enable transmission
Transmit buffer empty flag
Set this bit to "1" to enable reception
Reception complete flag
Invalid
Set to "0"
Set to "1"
Bus busy flag
Set to "0"
2
C Mode Functions
See Table 17.13 I
Set to "0"
Set this bit to "1" to have SCLi output
fixed to "L" at the falling edge of the 9th
bit of clock
Set to "0"
Set this bit to "1" to initialize UARTi at
start condition detection
Set this bit to "1" to have SCLi output
forcibly pulled low
Set this bit to "1" to disable SDAi output
Set to "0"
Set to "0"
2
C Mode Functions
See Table 17.13 I
Set the amount of SDAi digital delay
17. Serial I/O
Slave
(2)
2
C Mode Functions
2
C Mode Functions
2
C mode.
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