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M16C/62P Group (M16C/62P, M16C/62PT)
SDAi
ACKD register
Noise
Filter
SCLi
Noise
Filter
This diagram applies to the case where the SMD2 to SMD0 bits in the UiMR register = 010b and the IICM bit in the UiSMR register = 1.
IICM
IICM2, SWC, ALS, SWC2, SDHI : Bit in UiSMR2 register
STSPSEL, ACKD, ACKC
i=0 to 2
NOTES :
1. If the IICM bit = 1, the pin can be read even when the PD6_2, PD6_6 or PD7_1 bit = 1 (output mode).
2
Figure 17.21 I
C Mode Block Diagram
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
STSPSEL=1
Delay
circuit
STSPSEL=0
ACK=1
ACK=0
SDHI
ALS
D
Arbitration
Q
T
Start condition
detection
Stop condition
detection
Falling edge
detection
IICM=0
R
Port register
I/O port
Q
Internal clock
STSPSEL=0
UARTi
IICM=1
External
STSPSEL=1
clock
: Bit in UiSMR register
: Bit in UiSMR4 register
page 181
f o
3
6
4
Start and stop condition generation block
SDA(STSP)
SCL(STSP)
IICM2=1
Transmission
register
UARTi
Reception register
UARTi
S
Bus
Q
R
busy
D
Q
T
D
Q
ACK
T
(1)
9th bit
SWC2
CLK
control
UARTi
9th bit falling edge
R
S
SWC
DMA0, DMA1 request
(UART1: DMA0 only)
UARTi transmit,
NACK interrupt
request
IICM=1 and
IICM2=0
DMA0
(UART0, UART2)
IICM2=1
UARTi receive,
ACK interrupt request,
DMA1 request
IICM=1 and
IICM2=0
NACK
Start/stop condition detection
interrupt request
17. Serial I/O
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