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M16C/62P Group (M16C/62P, M16C/62PT)
14.2 DMA Transfer Cycles
Any combination of even or odd transfer read and write addresses is possible. Table 14.2 shows the
number of DMA transfer cycles. Table 14.3 shows the Coefficient j, k.
The number of DMAC transfer cycles can be calculated as follows:
No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k
Table 14.2 DMA Transfer Cycles
Transfer Unit
8-bit Transfers
(DMBIT= 1)
16-bit Transfers
(DMBIT= 0)
NOTES:
– : This condition dose not exist.
Table 14.3 Coefficient j, k
Internal Area
Internal ROM, RAM
No Wait With Wait
j
1
2
k
1
2
NOTES:
1. Depends on the set value of CSE register.
2. Depends on the set value of PM20 bit in the PM2 register.
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
Bus Width
Access Address
16-bit
Even
(BYTE= L)
Odd
8-bit
Even
(BYTE = H)
Odd
16-bit
Even
(BYTE = L)
Odd
8-bit
Even
(BYTE = H)
Odd
SFR
(2)
(2)
1-Wait
2-Wait
No Wait
2
3
2
3
page 117
f o
3
6
4
Single-Chip Mode
No. of Read No. of Write No. of Read No. of Write
Cycles
1
1
—
—
1
2
—
—
Separate Bus
With Wait
1 Wait
2 Waits
1
2
3
2
2
3
Memory Expansion Mode
Microprocessor Mode
Cycles
Cycles
1
1
1
1
—
1
—
1
1
1
2
2
—
2
—
2
External Area
Multiplex Bus
(1)
With Wait
3 Waits
1 Wait
2 Waits
4
3
4
3
14. DMAC
Cycles
1
1
1
1
1
2
2
2
(1)
3 Waits
3
4
3
4
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