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M16C/62P Group (M16C/62P, M16C/62PT)
Memory Expansion Mode, Microprocessor Mode
(
for 3-wait setting and external area access
Read timing
BCLK
t
30ns.max
CSi
ADi
BHE
t
d(BCLK-ALE)
30ns.max
ALE
RD
DBi
Hi-Z
Write timing
BCLK
t
30ns.max
CSi
t
30ns.max
ADi
BHE
t
d(BCLK-ALE)
30ns.max
ALE
WR, WRL
WRH
DBi
1
t
cyc=
f(BCLK)
Measuring conditions
• V
=V
=3V
CC1
CC2
• Input timing voltage
• Output timing voltage : V
Figure 23.19 Timing Diagram (7)
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
)
t
cyc
d(BCLK-CS)
t
d(BCLK-AD)
30ns.max
t
h(BCLK-ALE)
-4ns.min
t
d(BCLK-RD)
30ns.max
(3.5 X tcyc-60)ns.max
t
cyc
d(BCLK-CS)
d(BCLK-AD)
t
h(BCLK-ALE)
-4ns.min
t
d(BCLK-WR)
30ns.max
t
d(BCLK-DB)
40ns.max
Hi-Z
: V
=0.6V, V
=2.4V
IL
IH
=1.5V, V
=1.5V
OL
OH
page 310
f o
3
6
4
23. Electrical Characteristics (M16C/62P)
t
ac2(RD-DB)
t
su(DB-RD)
50ns.min
t
h(WR-AD)
(0.5 X tcyc-10)ns.min
t
d(DB-WR)
t
h(WR-DB)
(2.5 X tcyc-40)ns.min
(0.5 X tcyc-10)ns.min
V
= V
CC1
CC2
t
h(BCLK-CS)
4ns.min
t
h(BCLK-AD)
4ns.min
t
h(RD-AD)
0ns.min
t
h(BCLK-RD)
0ns.min
t
h(RD-DB)
0ns.min
t
h(BCLK-CS)
4ns.min
t
h(BCLK-AD)
4ns.min
t
h(BCLK-WR)
0ns.min
t
h(BCLK-DB)
4ns.min
= 3V
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